Memory structure comprising scratchpad memory

Memory hierarchy for a system-in-package, the memory hierarchy being directly connectable to a processor via a memory management unit configured to translate a virtual address sent by the processor into a physical address, the memory hierarchy having a data cache memory and a memory structure, the memory structure having at least a level 1 (L1) memory array comprising at least one cluster having one or more banks of scratchpad memory,

• wherein the memory hierarchy comprises a first data access controller configured to manage one or more of the banks of scratchpad memory of at least one of the clusters of the L1 memory array, comprising a data port configured to receive at least one physical address and configured to check at run time, for each received physical address, bits of the received physical address to see whether the physical address is present in the one or more banks of the at least one cluster of the L1 memory array and, if so, as a part of the managing, to forward a data request to one or more banks of scratchpad memory where the physical address is required, and if not, to forward the physical address to a cache controller configured to steer the data cache memory,
• wherein the memory structure further comprises a level 2 (L2) memory array comprising at least one cluster having one or more banks of scratchpad memory,
• wherein the memory structure further comprises a second data access controller configured to manage one or more of the banks of at least one of the clusters of the L2 memory array, comprising a second data port configured to receive at least one physical address from the first data access controller and configured to check, for each received physical address, whether the physical address is present in the one or more banks of the at least one cluster of the L2 memory array and, if so, to forward a data request to one or more banks of the L2 memory array where the physical address is required,
• wherein the memory hierarchy further comprises the memory management unit, wherein the memory management unit is configured for a page allocation strategy with at least two page sizes determined based on at least one page size bit, and where deciding on which page size to use is based on profiling of an object code and binary code by the data access controller, the profiling comprising an analysis of a number of accesses to a stack frame per function invocation, frame size and time between consecutive function calls.