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US 10,592,409 B2Granted
Memory system and method for controlling nonvolatile memory
AssigneeToshiba Memory Corporation
InventorShinichi Kanno
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.
Claims14
A memory system connectable to a host, comprising:
- a plurality of nonvolatile memory dies each including a plurality of blocks;
- and
- a controller electrically connected to the nonvolatile memory dies and configured to manage a plurality of parallel units each including blocks belonging to different nonvolatile memory dies,
- each of the parallel units having a unique first block address, each of the blocks in each nonvolatile memory die having a unique second block address, the second block addresses of blocks to be included in each parallel unit being determined from the first block address of each parallel unit, based on a mathematical rule, wherein
- the controller is configured:
- to manage defect information holding at least 1-bit information indicative of being available or unavailable for each block in each parallel unit;
- and
- when receiving from the host a write request designating a third address to identify first data to be written, to select one block from undefective blocks included in one parallel unit as a write destination block by referring to the defect information, to determine a write destination location in the selected block, to write the first data to the write destination location, and to notify the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.
5 more elements
A memory system connectable to a host, comprising:
- a plurality of nonvolatile memory dies each including a plurality of blocks;
- and
- a controller electrically connected to the nonvolatile memory dies and configured to manage a plurality of parallel units each including blocks belonging to different nonvolatile memory dies,
- each of the parallel units having a unique first block address, each of the blocks in each nonvolatile memory die having a unique second block address, the second block addresses of blocks to be included in each parallel unit being determined from the first block address of each parallel unit, based on a mathematical rule, wherein
- the controller configured:
- to manage defect information holding at least 1-bit information indicative of being available or unavailable for each block in each parallel unit;
- when receiving from the host a write request designating a third address to identify first data to be written, to select an undefective block in a parallel unit to be written as a write destination block by (i) selecting one block from undefective blocks included in the parallel unit by referring to the defect information, or (ii) by executing address translation of translating an address of a block to be accessed so as to allow all undefective blocks in the parallel unit to be logically arranged sequentially from a leading part of the parallel unit, based on the defect information;
- to determine a write destination location in the selected block;
- to write the first data to the write destination location;
- and
- to notify the host of a physical address indicative of both of the selected block and the write destination location, and the third address, or a physical address indicative of both of the block to be accessed before the address translation and the write destination location, and the third address.
8 more elements
A method of controlling a plurality of nonvolatile memory dies each including a plurality of blocks, the method comprising:
- managing a plurality of parallel units each including blocks belonging to different nonvolatile memory dies;
- each of the plural parallel units having a unique first block address, each of the blocks in each nonvolatile memory die having a unique second block address, the second block addresses of blocks to be included in each parallel unit being determined from the first block address of each parallel unit, based on a mathematical rule,
- managing defect information holding at least 1-bit information indicative of being available or unavailable for each block in each parallel unit;
- and
- executing, when receiving from a host a write request designating a third address to identify first data to be written, an operation of selecting one block from undefective blocks included in one parallel unit as a write destination block by referring to the defect information, an operation of determining a write destination location in the selected block, an operation of writing the first data to the write destination location, and an operation of notifying the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.
2 more elements
Dependencies are inferred from the claim text.