Functional interconnect redundancy in cache coherent systems

A system-on-chip (SoC) comprising:

• at least one agent;
• memory, including coherent memory, in communication with the agent;
• and a coherent interconnect in communication with the memory and the agent, the interconnect comprising:
• a transport network in communication with the agent;
• a plurality of coherent interconnect elements in communication with the transport network, the plurality of coherent interconnect elements including:
• a plurality of functional coherent interconnect elements;
• a plurality of duplicate checker coherent interconnect elements, wherein a driver of an input port of each of the selected set of functional coherent interconnect elements is also used to drive an input port of each of the duplicate checker coherent interconnect elements at least one clock cycle later;
• and
• a controller in communication with each of the selected set of functional
• coherent interconnect elements and each of the duplicated checker coherent interconnect elements,
• wherein each output port of each of the selected set of functional coherent interconnect elements is delayed at least one clock cycle and sent to the controller,
• wherein each output port of each of the duplicate checker coherent interconnect elements is sent to the controller without being delayed, wherein the controller compares outputs of each of the selected set of functional coherent interconnect elements with all the outputs of each of the duplicated checker coherent interconnect elements, and
• wherein the controller determines, based on the comparison, if a mismatch is found between the output of any one of the selected set of functional coherent interconnect elements and the output of the corresponding duplicate checker coherent interconnect elements.

A method comprising:

• sending transactions from an agent to a functional coherent interconnect;
• sending read and write transactions from the agent, after a delay, to a duplicate coherent interconnect, wherein the functional coherent interconnect and the duplicate coherent interconnect are identical;
• sending all outputs of functional coherent interconnect, after the delay, to a comparator;
• sending all outputs of the duplicate coherent interconnect, without the delay, to the comparator;
• comparing corresponding inputs at the comparator, one from the functional coherent interconnect after a delay and another from the checker coherent interconnect without a delay, to determine if there is a mismatch between the corresponding inputs;
• and
• signaling the SoC, using a controller, that an error has occurred when the mismatch is found so that the SoC can take further action to mitigate the consequence of the error.