Streaming engine with error detection, correction and restart

A digital data processor comprising:

• an instruction memory to store instructions each specifying a data processing operation and at least one operand;
• an instruction decoder connected to the instruction memory for sequentially recalling instructions from the instruction memory and determining the specified data processing operation and the specified at least one operand;
• a data register file connected to the instruction decoder;
• at least one functional unit connected to the data register file and the instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results to the data register file;
• a streaming engine connected to the instruction decoder operable in response to a stream start instruction to recall from a memory a stream of a plurality of data elements, the streaming engine including:
• an address generator for generating stream memory addresses corresponding to the stream of the plurality of data elements;
• a stream buffer receiving and temporarily storing data elements corresponding to the stream memory addresses;
• and
• a stream head register storing a data element of the stream next to be used by the at least one functional unit;
• a first parity bit generator receiving the plurality of data elements from the memory, having an output connected to the streaming engine, the first parity bit generator configured to form first parity bits from the plurality of data elements wherein the stream buffer stores both the plurality of data elements of the stream and the first parity bits;
• and
• a second parity bit generator receiving the stored stream and the first parity bits from the streaming engine before supply to the at least one functional unit, the second parity bit generator operable to:
• form second parity bits from the plurality of data elements output from the streaming engine;
• compare the first parity bits with the second parity bits;
• and
• signal a parity fault if the first parity bits do not match the second parity bits;
• and
• wherein the at least one functional unit is responsive to a stream operand instruction to receive at least one operand from the stream head register.