System and method for information handling system input/output resource management
AssigneeDell Products L.P.
InventorsJohn C. Beckett, Robert W. Hormuth
Life of this patent
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Abstract
An information handling system includes a processor complex with a root complex that provides N serial data lanes, where N is an integer. The information handling system also includes boot process logic that determines that a device is coupled to X of the serial data lanes, where X is an integer less than N, determines that no device is coupled to Y of the serial data lanes, where Y is an integer less than or equal to N−X, and allocates a portion of bus resources of the root complex to the device, the portion being greater (X+Y)/N.
Claims20
An information handling system, comprising:
- a processor complex including a Peripheral Component Interconnect-Express (PCIe) root complex that provides N serial data lanes, where N is an integer;
- and
- boot process logic configured to enumerate the root complex during a system boot process for the information handling system, wherein in enumerating the root complex the boot process logic:
- determines that a device is coupled to X of the serial data lanes, where X is an integer less than N;
- determines that no device is coupled to Y of the serial data lanes, where Y is an integer less than or equal to N−X;
- and
- allocates a portion of bus resources of the root complex to the device, the portion being greater than or equal to (X+Y)/N.
A method, comprising:
- providing, on a Peripheral Component Interconnect-Express (PCIe) root complex of a processor complex of an information handling system, N serial data lanes, where N is an integer;
- determining, by boot process logic of the information handling system configured to enumerate the root complex during a system boot process for the information handling system, that a device is coupled to X of the serial data lanes, where X is an integer less than N;
- determining, by the boot process logic, that no device is coupled to Y of the serial data lanes, where Y is an integer less than or equal to N−X;
- and
- allocating, by the boot process logic, a portion of bus resources of the root complex to the device, the portion being greater than or equal to (X+Y)/N.
An information handling system, comprising:
- a processor complex including a Peripheral Component Interconnect-Express (PCIe) root complex that provides N serial data lanes, where N is an integer;
- and
- boot process logic configured to enumerate the root complex during a system boot process for the information handling system, wherein in enumerating the root complex the boot process logic:
- determines that a first device is coupled to X of the serial data lanes, where X is an integer less than N;
- allocates a first portion of bus resources to the first device, the first portion being X/N of a total amount of bus resources of the root complex;
- determines that a second device is coupled to Y of the serial data lanes, where Y is an integer less than X−N;
- determines that no device is coupled to Z of the serial data lanes, where Z is a non-zero integer less than or equal to N−X−Y;
- and allocates a portion of bus resources of the root complex to the device, the portion being greater than or equal to (Y+Z)/N.
Dependencies are inferred from the claim text.