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US 10,592,281 B1Granted
Wait optimizer for recording an order of first entry into a wait mode by a virtual central processing unit
AssigneeAmazon Technologies, Inc.
InventorAli Ghassan Saidi
Life of this patent
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Abstract
A wait optimizer circuit can be coupled to a processor to monitor an entry of a virtual CPU (vCPU) into a wait mode to acquire a ticket lock. The wait optimizer can introduce an amount of delay, while the vCPU is in the wait mode, with an assumption that the spinlock may be resolved before sending a wake up signal to the processor for rescheduling. The wait optimizer can also record a time stamp only for a first entry of the vCPU from a plurality of entries into the wait mode within a window of time. The time stamps for vCPUs contending for the same ticket lock can be used by a hypervisor executing on the processor for rescheduling the vCPUs.
Claims20
An apparatus comprising:
- a processor, a hypervisor, and virtual CPUs (vCPUs);
- the processor configured to execute instructions for the hypervisor and vCPUs, wherein
- each vCPU from the vCPUs is configured to enter a respective wait mode while waiting to acquire a same ticket lock;
- and
- the hypervisor is configured to schedule each vCPU from the vCPUs for execution in an order in which each vCPU from the vCPUs first entered the respective wait mode, wherein a threshold value for each vCPU from the vCPUs is programmed in a respective window of time register by the hypervisor;
- and
- an integrated circuit coupled to the processor for recording an order of entering the respective wait mode by each vCPU from the vCPUs for a first time only within a respective window of time, the respective window of time having a sufficient duration for each vCPU from the vCPUs contending for the same ticket lock to acquire and release the same ticket lock, wherein for each vCPU from the vCPUs the integrated circuit is configured to:
- monitor a signal from the processor of the apparatus to detect an entry of a respective vCPU into the respective wait mode;
- record a time stamp and a ticket lock address associated with the respective vCPU when the entry of the respective vCPU into the respective wait mode within the respective window of time is a first entry into the respective wait mode, wherein the respective window of time is initiated upon the first entry of the respective vCPU into the respective wait mode, and ends upon a wait counter that starts counting upon the first entry and reaches a value equal to the threshold value for the respective window of time;
- while the respective vCPU is in the respective wait mode, count using a respective timer until the respective timer reaches a respective predetermined value, wherein the respective predetermined value for the respective vCPU is programmed in a delay register by the hypervisor;
- and
- upon the respective timer reaching the respective predetermined value, send an event signal to the processor to wake up the respective vCPU to compare a first value stored at the ticket lock address with a second value stored in a memory or stored in a register by the respective vCPU,
- wherein the hypervisor is configured to schedule each vCPU from the vCPUs to execute in the order based on an earliest time stamp associated with each vCPU from the vCPUs and, when the respective vCPU has the second value stored in the memory or stored in the register that matches the first value stored at the ticket lock address, the respective vCPU acquires the ticket lock.
10 more elements
An integrated circuit coupled to an apparatus having a processor, a hypervisor, and virtual CPUs (vCPUs);
- the processor being configured to execute instructions for the hypervisor and vCPUs,
- wherein each vCPU from the vCPUs is configured to enter a respective wait mode while waiting to acquire a same ticket lock;
- wherein the hypervisor is configured to schedule each vCPU from the vCPUs for execution in an order in which each vCPU from the vCPUs first entered the respective wait mode, wherein a threshold value for each vCPU from the vCPUs is programmed in a respective window of time register by the hypervisor;
- and
- wherein the integrated circuit is configured to record an order of entering the respective wait mode by each vCPU from the vCPUs for a first time only within a respective window of time, the respective window of time having a sufficient duration for each vCPU from the vCPUs contending for the same ticket lock to acquire and release the same ticket lock, wherein the integrated circuit comprises:
- an event monitor module configured to monitor a signal from the processor to detect an entry of a respective vCPU from the vCPUs into a respective wait mode;
- a timestamp recorder module configured to record a time stamp and a ticket lock address associated with the respective vCPU when the entry of the respective vCPU into the respective wait mode within the respective window of time is a first entry into the respective wait mode, wherein the respective window of time is initiated upon the first entry of the respective vCPU into the respective wait mode from a plurality of entries into the respective wait mode within the respective window of time, and ends upon a wait counter that starts counting upon the first entry and reaches a value equal to the threshold value for the respective window of time;
- a respective timer configured to count, while the respective vCPU is in the respective wait mode, until the respective timer reaches a predetermined respective predetermined value, wherein the respective predetermined value for the respective vCPU is programmed in a delay register by the hypervisor;
- and
- an event signal generator module configured to send an event signal to the processor to wake up the respective vCPU from the respective wait mode to compare a first value stored at the ticket lock address with a second value stored in a memory or stored in a register by the respective vCPU, upon the respective timer reaching the respective predetermined value,
- wherein the hypervisor is configured to schedule each vCPU from the vCPUs to execute in the order based on an earliest time stamp associated with each vCPU from the vCPUs, and when the respective vCPU has the second value stored in the memory or stored in the register that matches the first value stored at the ticket lock address, the respective vCPU acquires the ticket lock.
8 more elements
A method executed by an integrated circuit coupled to an apparatus having a processor, a hypervisor, and virtual CPUs (vCPUs),
- wherein the processor is configured to execute instructions for the hypervisor and vCPUs, wherein
- each vCPU from the vCPUs is configured to enter a respective wait mode while waiting to acquire a same ticket lock;
- wherein the hypervisor is configured to schedule each vCPU from the vCPUs for execution in an order in which each vCPU from the vCPUs first entered the respective wait mode, wherein a threshold value for each vCPU from the vCPUs is programmed in a respective window of time register by the hypervisor;
- and
- wherein the method comprises:
- monitoring a signal from the processor of the apparatus to detect an entry of a respective vCPU into the respective wait mode;
- recording a time stamp and a ticket lock address associated with the respective vCPU when the entry of the respective vCPU into the respective wait mode within a respective window of time is a first entry from a plurality of entries into the respective wait mode within the respective window of time, the respective window of time having a sufficient duration for each vCPU from the vCPUs contending for the same ticket lock to acquire and release the same ticket lock wherein the respective window of time is initiated upon the first entry of the respective vCPU into the respective wait mode, and ends upon a wait counter that starts counting upon the first entry and reaches a value equal to the threshold value for the respective window of time;
- while the respective vCPU is in the respective wait mode, counting using a respective timer until the respective timer reaches a respective predetermined value, wherein the respective predetermined value for the respective vCPU is programmed in a delay register by the hypervisor;
- and
- upon the respective timer reaching the respective predetermined value, sending an event signal to the processor to wake up the respective vCPU to compare a first value stored at the ticket lock address with a second value stored in a memory or stored in a register by the respective vCPU,
- wherein the hypervisor is configured to schedule each vCPU from the vCPUs to execute in an order based on an earliest time stamp associated with each vCPU from the vCPUs, and when the respective vCPU has the second value stored in the memory or stored in the register that matches the first value stored at the ticket lock address, the respective vCPU acquires the ticket lock.
8 more elements
Dependencies are inferred from the claim text.