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US 10,592,252 B2Granted
Efficient instruction processing for sparse data
AssigneeMicrosoft Technology Licensing, LLC
InventorsTrishul A. Chilimbi, Olatunji Ruwase, Vivek Seshadri
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Abstract
Efficient instruction processing for sparse data includes extensions to a processor pipeline to identify zero-optimizable instructions that include at least one zero input operand, and bypass the execute stage of the processor pipeline, determining the result of the operation without executing the instruction. When possible, the extensions also bypass the writeback stage of the processor pipeline.
Claims14
A method implemented according to a processor pipeline, the method comprising:
- during execution of a code loop, fetching an instruction to be processed;
- examining a zero optimized table to determine whether the instruction is mapped to an annotation in a zero optimized annotation table that includes annotations to instructions in the code loop previously identified as zero-optimizable, the zero optimized table including data that indicates conditions under which the annotations can be applied;
- determining, based on inclusion of an annotation to the instruction in the zero optimized annotation table, that the instruction to be processed is a zero-optimizable instruction, the annotation to the instruction having one or more associated conditions under which the annotation can be applied;
- accessing a register file to determine whether the one or more associated conditions under which the annotation to the instruction can be applied are met;
- and,
- based on the one or more associated conditions being met, processing the instruction based on the annotation as read from the zero optimized annotation table.
3 more elements
A processor comprising:
- a processor pipeline to direct performance of fetch, decode, execute, writeback, and commit stages;
- and
- extensions to the processor pipeline, the extensions to the processor pipeline configured to detect and direct processing of zero-optimizable instructions, the extensions comprising
- a loop optimizer configured to generate and store annotations to zero-optimizable instructions in a zero optimized annotation table and to maintain a zero optimized table that stores mappings between the zero-optimizable instructions and corresponding annotations and that further indicates conditions under which the annotations can be applied;
- and
- an optimized code fetcher configured to fetch an instruction, examine the zero optimized annotation table to determine whether the instruction being fetched is mapped in the zero optimized table to a corresponding annotation and, in response to the instruction being mapped to a corresponding annotation, access a register file to determine whether one or more associated conditions under which the corresponding annotation to the instruction can be applied are met, wherein, if the one or more associated conditions are met, the instruction is processed based on the corresponding annotation as read from the zero optimized annotation table.
3 more elements
A device comprising:
- memory storing:
- an instruction cache configured to store a loop of instructions to be processed;
- a zero optimized annotation table configured to store annotations to zero-optimizable ones of the instructions;
- and
- a zero optimized table configured to store mappings between the zero-optimizable instructions and corresponding annotations and conditions under which the annotations can be applied;
- and
- a processor, communicatively coupled to the instruction cache, the zero optimized table, and the zero optimized annotation table, wherein the processor is configured to:
- fetch an instruction from the instruction cache;
- determine, based on whether the instruction is mapped to an annotation in the zero optimized annotation table, whether the instruction is a zero-optimizable instruction;
- when the processor determines that the instruction is a zero-optimizable instruction, determine whether one or more associated conditions under which the corresponding annotation can be applied are met;
- and
- when the one or more associated conditions are met, process the instruction based on the annotation as read from the zero optimized annotation table.
9 more elements
Dependencies are inferred from the claim text.