Selective suppression of instruction translation lookaside buffer (ITLB) access
AssigneeInternational Business Machines Corporation
InventorsMichael K. Gschwind, Valentina Salapura
Life of this patent
Estimating the term…
Abstract
Processing of an instruction fetch from an instruction cache is provided, which includes: determining whether the next instruction fetch is from a same address page as a last instruction fetch from the instruction cache; and based, at least in part, on determining that the next instruction fetch is from the same address page, suppressing for the next instruction fetch an instruction address translation table access, and comparing for an address match results of an instruction directory access for the next instruction fetch with buffered results of a most-recent, instruction address translation table access for a prior instruction fetch from the instruction cache.
Claims8
A method of processing an instruction fetch from an instruction cache, the method comprising:
- determining for a next instruction fetch whether the next instruction fetch is from a same address page as a last instruction fetch from the instruction cache;
- based, at least in part, on determining that the next instruction fetch is from the same address page, suppressing for the next instruction fetch an instruction address translation table access, and comparing for an address match results of an instruction directory access for the next instruction fetch with buffered results of a most-recent, instruction address translation table access for a prior instruction fetch from the instruction cache;
- and
- refraining from the suppressing where there has been an invalidation action effecting the same address page, causing the same address page to no longer be valid, the invalidation action resulting in a suppress signal being negated.
Dependencies are inferred from the claim text.