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US 10,592,247 B2Granted
Arithmetic circuit and control method with full element permutation and element concatenate shift left
AssigneeFujitsu Limited
InventorTomonori Tanaka
Life of this patent
Estimating the term…
Abstract
An arithmetic circuit comprises first to N-th, N being an integer equal to or larger than two, element circuits respectively including: input circuits which input first operand data and second operand data; and element data selectors which select operand data of any one of the element circuits on the basis of a request element signal; and a data bus which supplies the operand data from the input circuits to the element data selectors. When a control signal is in a first state, the element data selectors select, on the basis of the request element signal included in the second operand data, the first operand data of any of the element circuits and output the first operand data.
Claims6
An arithmetic circuit comprising:
- first to N-th, N being an integer equal to or larger than two, element circuits each of which includes:
- input circuits configured to input first operand data and second operand data;
- and
- an element data selector configured to select the first operand data or the second operand data of any one of the first to N-th element circuits on the basis of a request element signal;
- and
- a data bus, provided in common to the first to N-th element circuits, configured to supply the first operand data or the second operand data input by each of the first to N-th element circuits to the element data selector of each of the first to N-th element circuits, wherein:
- each of the first to N-th element circuits has a corresponding element number,
- each of the first to N-th element circuits includes:
- an operand selector configured to:
- select, when a control signal is in a first state, the first operand data to output to the data bus, and
- select, when the control signal is in a second state, on the basis of an operand switch signal that indicates whether or not a shift amount, which is common for the first to N-th element circuits, is larger than the corresponding element number, the first operand data or the second operand data to output to the data bus, and
- the element data selector in each of the first to N-th element circuits:
- selects, when the control signal is in the first state, on the basis of a first request element signal included in the second operand data, the first operand data of any one of the first to N-th element circuits, and
- selects, when the control signal is in the second state, on the basis of a second request element signal that is generated by adding the corresponding element number to the shift amount, the first operand data or the second operand data selected by the operand selector of any one of the first to N-th element circuits.
11 more elements
A control method for an arithmetic circuit including:
- first to N-th, N being an integer equal to or larger than two, Single Instruction Multiple Data (SIMD) arithmetic elements each of which includes:
- a first operand register to which first operand data is input;
- a second operand register to which second operand data is input;
- an arithmetic operator configured to receive inputs of the first operand data and the second operand data and perform an arithmetic operation on the first operand data and the second operand data;
- a result register configured to store an arithmetic result output by the arithmetic operator;
- and
- an element data selector configured to select the first operand data or the second operand data of any one of the first to N-th SIMD arithmetic elements on the basis of a request element signal;
- and
- a data bus, provided in common to the first to N-th SIMD arithmetic elements, configured to supply the first operand data or the second operand data input by each of the first to N-th SIMD arithmetic elements to the element data selector of each of the first to N-th SIMD arithmetic elements,
- the control method comprising:
- an operand selector in each of the first to N-th SIMD arithmetic elements:
- selecting when a control signal is in a first state, the first operand data to output to the data bus, and
- selecting, when the control signal is in a second state, on the basis of an operand switch signal that indicates whether or not a shift amount, which is common for the first to N-th SIMD arithmetic elements, is larger than a corresponding element number that each of the first N-th SIMD arithmetic elements has, the first operand data or the second operand data to output to the data bus, and
- the element data selector in each of the first to N-th SIMD arithmetic elements:
- selecting, when the control signal is in the first state, on the basis of a first request element signal included in the second operand data, the first operand data of any one of the first to N-th SIMD arithmetic elements, and
- selecting, when the control signal is in the second state, on the basis of a second request element signal that is generated by adding the corresponding element number to the shift amount, the first operand data or the second operand data selected by the operand selector of any one of the first to N-th SIMD arithmetic elements.
13 more elements
Dependencies are inferred from the claim text.