Low latency execution of floating-point record form instructions
AssigneeInternational Business Machines Corporation
InventorsBrian J. D. Barrick, Maarten J. Boersma, Niels Fricke, Michael J. Genden
Life of this patent
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Abstract
A computer processing system is provided. The computer processing system includes a processor configured to crack a record form FP instruction into two internal instructions. A first one of the two internal instructions executes out-of-order to compute a target FP register and a second one of the two internal instructions executes in-order to compute a condition register (CR) to improve a processing speed of the record form FP instruction.
Claims10
A computer processing system, comprising:
- a processor configured to crack a record form Floating Point (FP) instruction into two internal instructions independent of a machine state, wherein a first one of the two internal instructions executes out-of-order to compute a target FP register and a second one of the two internal instructions executes in-order to compute a condition register (CR) to improve a processing speed of the record form FP instruction.
A computer program product for record form Floating-Point (FP) instruction execution, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform a method comprising:
- cracking, by a processor, a record form FP instruction into two internal instructions independent of a machine state, wherein a first one of the two internal instructions executes out-of-order to compute a target FP register and a second one of the two internal instructions executes in-order to compute a condition register (CR) to improve a processing speed of the record form FP instruction.
Dependencies are inferred from the claim text.