Instructions and logic to provide SIMD SM3 cryptographic hashing functionality

A processor comprising:

• a decode stage to decode a first instruction for a single instruction multiple data (SIMD) SM3 four message expansion operation, the first instruction to specify a first source data operand set, and a second source data operand set;
• and
• one or more execution units coupled with the decode stage, the one or more execution units, responsive to the decoded first instruction, to:
• perform four SM3 message expansions of four new 32-bit message words from the first and second source data operand sets;
• and
• store a result of the first instruction in a SIMD destination register.

A processor comprising:

• a plurality of vector registers that each are to store at least 512-bits;
• a decode stage to decode a first instruction for a single instruction multiple data (SIMD) set of SM3 hash rounds, the first instruction to specify a 512-bit intermediate hash value input operand that is to have two 256-bit starting states, and a 512-bit source data operand set, wherein at least one of the 512-bit intermediate hash value input operand, and the 512-bit source data operand set, are to be stored in the plurality of vector registers;
• and
• one or more execution units coupled with the plurality of vector registers and coupled with the decode stage, the one or more execution units, responsive to the decoded first instruction, to:
• store a result of the first instruction in a destination vector register of the plurality of vector registers, the result to include a first SM3 hash value that is based on one of the two 256-bit starting states and a second SM3 hash value that is based on another of the two 256-bit starting states.