Branch type logging in last branch registers

A system comprising:

• a memory to store a branch instruction, wherein a type of the branch instruction is one of a conditional instruction, an unconditional instruction, an indirect jump instruction, a direct jump instruction, a direct call instruction, an indirect call instruction, a return instruction, or a far instruction;
• a processor comprising:
• an instruction fetcher to fetch the branch instruction from the memory;
• an execution circuit to execute the branch instruction;
• a retirement circuit coupled to the execution circuit, the retirement circuit comprising a LBR counter having a counter field to iterate with each cycle of the processor and a type field to store a value indicating a type of the branch instruction;
• and
• a last branch record (LBR) structure communicably coupled to the LBR counter and comprising a plurality of LBR entries, wherein an LBR entry of the plurality of LBR entries comprises:
• an address instruction pointer (IP) of the branch instruction executed by the processor;
• an address IP of a target of the branch instruction;
• and
• an elapsed time field that stores a value of the LBR counter when the LBR entry is created;
• and
• a type field to store a multi-bit value corresponding to the type stored in the LBR counter when the branch instruction is retired by the retirement circuit, wherein the type is determined using a key from the branch instruction to query a data structure to identify the multi-bit value corresponding to the type of the branch instruction.

A hardware-implemented method comprising:

• executing, by a processor, a first branch instruction of a set of instructions for a program;
• recording, by the processor in a first entry of a last branch record (LBR) structure, information about the first branch instruction;
• sampling a cycle count of a LBR counter to obtain a first cycle count;
• recording the first cycle count in the first entry when the first branch instruction is retired;
• determining a first type of the first branch instruction associated with a first keyword in the first branch instruction, the first keyword being associated with the first type of the first branch instruction;
• querying a data structure using the first keyword to identify a first multi-bit value representative of the first type of the first branch instruction;
• recording the first multi-bit value representative of the first type of the first branch instruction in the first entry of the LBR structure;
• executing, by the processor, a second branch instruction of the set of instructions for the program;
• recording, by the processor in a second entry of the LBR structure, information about the second branch instruction;
• sampling the cycle count of the LBR counter to obtain a second cycle count;
• recording the second cycle count in the second entry when the second branch instruction is retired;
• determining a second type of the second branch instruction associated with a second keyword in the second branch instruction, the second keyword being associated with the second type of the second branch instruction;
• querying a data structure using the second keyword to identify a second multi-bit value representative of the second type of the second branch instruction;
• and
• recording the second multi-bit value representative of the second type of the second branch instruction in the second entry.