Computer system and method for parallel program code optimization and deployment

A computer-implemented method for deploying a compile-time optimized parallelized program to a processing device with a plurality of processing units, the method comprising:

• receiving an initial program code, the initial program code implementing an algorithm wherein the algorithm is to be executed by the processing device;
• extracting, from the initial program code, a hierarchical task representation wherein each node of the hierarchical task representation corresponds to a potential unit of execution, wherein a root node of the hierarchical task representation represents the initial program code and each child node represents a sub-set of units of execution of its respective parent node;
• applying to the hierarchical task representation a plurality of pre-defined parallelization rules associated with the processing device to automatically adjust the hierarchical task representation by assigning units of execution to one or more processing units of the processing device and by inserting communication tasks or synchronization tasks such that the adjusted hierarchical task representation reflects parallel program code for communicating or synchronizing between two or more of the processing units corresponding to the processing device;
• generating a visual representation of the adjusted hierarchical task representation, wherein each node of at least a subset of nodes is represented by a user interface object and the user interface objects are arranged according to the respective parent-child relationships;
• receiving, for one or more interactive user interface objects, one or more user defined parallelization parameters modifying the arrangement of the interactive user interface objects of a scheduling view, wherein a plurality of interactive user interface objects have task length properties representing an execution time interval of the corresponding units of execution on a particular processing unit of the processing device;
• re-applying the pre-defined parallelization rules with the one or more user defined parallelization parameters to automatically generate a modified parallel program code for the processing device adjusted to the user defined parallelization parameters;
• and
• deploying the modified parallel program code to the processing device.

A computer program product comprising instructions that when loaded into a memory of a computing device and executed by at least one processor of the computing device cause the computing device to carry out optimizing operations, at compile time, the optimizing operations including:

• receiving an initial program code, the initial program code implementing an algorithm wherein the algorithm is to be executed by the processing device;
• extracting, from the initial program code, a hierarchical task representation wherein each node of the hierarchical task representation corresponds to a potential unit of execution, wherein the root node of the hierarchical task representation represents the initial program code and each child node represents a sub-set of units of execution of its respective parent node;
• applying, to the hierarchical task representation a plurality of pre-defined parallelization rules associated with the processing device to automatically adjust the hierarchical task representation by assigning units of execution to one or more processing units of the processing device and by inserting communication tasks or synchronization tasks such that the adjusted hierarchical task representation reflects parallel program code for communicating or synchronizing between two or more of the processing units corresponding to the processing device;
• generating a visual representation of the adjusted hierarchical task representation, wherein each node of at least a subset of nodes is represented by a user interface object and the user interface objects are arranged according to the respective parent-child relationships;
• receiving, for one or more interactive user interface objects, one or more user defined parallelization parameters modifying the arrangement of the interactive user interface objects of the scheduling view, wherein a plurality of interactive user interface objects have task length properties representing an execution time interval of the corresponding units of execution on a particular processing unit of the processing device;
• re-applying the pre-defined parallelization rules with the one or more user defined parallelization parameters to automatically generate a modified parallel program code for the processing device adjusted to the user defined parallelization parameters;
• and
• deploying the modified parallel program code to the processing device.