Charge-scaling multiplier circuit

A method of operating a multiplier circuit that uses charge-scaling to multiply a first N-bit binary number by a second N-bit binary number, the multiplier circuit fabricated within an integrated circuit (IC), the method comprising:

• resetting the multiplier circuit by drawing to ground, with at least one local reset device of the multiplier circuit, at least one local product node of the multiplier circuit;
• receiving, with a first set of N inputs of the multiplier circuit, a first N-bit binary number;
• receiving, with a second set of N inputs of the multiplier circuit, a second N-bit binary number;
• performing, with a set of AND gates of the multiplier circuit, logical AND operations upon combinations of bits of the first and of the second N-bit binary numbers;
• drawing, by applying results of the logical AND operations to a set of scaled capacitors of the multiplier circuit, a most significant (MS) local product node to an output voltage proportional to a product of the first and second N-bit binary numbers;
• and
• driving, with a unity gain amplifier, a product output node of the multiplier circuit to an output voltage of the MS local product node.

A design structure embodied on a non-transitory computer-readable storage medium readable by a machine used in design, manufacture, and simulation of an integrated circuit (IC) multiplier circuit, the design structure comprising elements that, when processed in a semiconductor manufacturing facility, produce an IC comprising:

• a multiplier circuit fabricated within an integrated circuit (IC), the multiplier circuit configured to draw a product output node to a voltage proportional to a product of two received N-bit binary numbers, the multiplier circuit including:
• a first set of N inputs configured to receive a first N-bit binary number, each input of the first set of N inputs indexed by an integer bit number “n” corresponding to each input's respective significance, where n is in a range between and including 0 and N−1;
• a second set of N inputs configured to receive a second N-bit binary number, each input of the second set of N inputs indexed by the integer bit number “n” corresponding to each input's respective significance;
• a plurality of sections including a most significant (MS) section, each section of the plurality of sections having a respective local product node and a local reset device configured to draw, in response to receiving a reset signal, the respective local product node to ground;
• at least one attenuation capacitor, each at least one attenuation capacitor having first and second terminals electrically interconnected to respective local product nodes of electrically adjacent sections of the plurality of sections;
• a unity gain amplifier configured to drive the product output node to a voltage equivalent to a voltage on an MS local product node of the MS section;
• a plurality of groups of AND gates, each group of the plurality of groups including at least one AND gate having inputs electrically connected to a unique combination of a first input of the first set of N inputs and a second input of the second set of N inputs, where the unique combination of the first input and the second input has a sum “m” of corresponding bit numbers of the first input and of the second input that is unique to each group of the plurality of groups, wherein the output of each AND gate within each group of the plurality of groups of AND gates is electrically connected to a first terminal of a respective scaled capacitor having a capacitance value equal to 2(m−1)* a unit capacitance value (CUNIT)/4, where “1” is a smallest sum of sums “m” corresponding to groups of AND gates located within a respective section, and wherein a second terminal of each scaled capacitor within a section is electrically connected to the local product node of that section;
• and
• a reference capacitor electrically connected to ground, and further electrically connected to a local product node of a least significant (LS) section of the plurality of sections, a value of the reference capacitor equal to CUNIT.