Dynamic variable precision computation
AssigneeAdvanced Micro Devices, Inc.
InventorsGreg Sadowski, Wayne Burleson
Life of this patent
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AssigneeAdvanced Micro Devices, Inc.
InventorsGreg Sadowski, Wayne Burleson
Estimating the term…
A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.
An apparatus comprising:
A method comprising:
An apparatus comprising:
Dependencies are inferred from the claim text.