Toggling modal transient memory access state

A computer system for facilitating processing in a computing environment, said computer system comprising:

• a memory;
• and
• a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
• determining that an application will enter an infrequent state of operation, the infrequent state of operation including a plurality of memory accesses that are to be infrequently processed;
• based on the determining, providing one or more instructions architecturally defined to toggle a transient mode state in the processor for a selected period within which the plurality of memory accesses are to be processed, the toggling allowing the processor to decline storing data to be accessed, via the plurality of memory accesses, in at least a portion of a cache hierarchy for the selected period, the toggling facilitating preserving at least a portion of data stored in the cache hierarchy that would otherwise be supplanted by the data to be accessed via the plurality of memory accesses, wherein the cache hierarchy includes a plurality of levels of cache and is separate from a main memory, and wherein execution of the one or more instructions comprises:
• activating a transient mode for the application executing in the computing environment for the selected period;
• processing, based on activating the transient mode for the application, the plurality of memory accesses, wherein the plurality of memory accesses are processed as transient accesses, and wherein at least one memory access of the plurality of memory accesses being processed as a transient access has storing of data in one or more levels of the cache hierarchy declined based on the activating of the transient mode;
• and
• deactivating, based on reaching the selected period, the transient mode for the application.

A computer-implemented method of facilitating processing in a computing environment, said computer-implemented method comprising:

• determining that an application will enter an infrequent state of operation, the infrequent state of operation including a plurality of memory accesses that are to be infrequently processed;
• based on the determining, providing one or more instructions architecturally defined to toggle a transient mode state in a processing circuit for a selected period within which the plurality of memory accesses are to be processed, the toggling allowing the processing circuit to decline storing data to be accessed, via the plurality of memory accesses, in at least a portion of a cache hierarchy for the selected period, the toggling facilitating preserving at least a portion of data stored in the cache hierarchy that would otherwise be supplanted by the data to be accessed via the plurality of memory accesses, wherein the cache hierarchy includes a plurality of levels of cache and is separate from a main memory, and wherein execution of the one or more instructions comprises:
• activating a transient mode for the application executing in the computing environment for the selected period;
• processing, based on activating the transient mode for the application, the plurality of memory accesses, wherein the plurality of memory accesses are processed as transient accesses, and wherein at least one memory access of the plurality of memory accesses being processed as a transient access has storing of data in one or more levels of the cache hierarchy declined based on the activating of the transient mode;
• and
• deactivating, based on reaching the selected period, the transient mode for the application.