Inherent adaptive trimming
AssigneeSanDisk Technologies LLC
InventorsAbhijeet Manohar, Daniel Tuers, Sathyanarayanan Subramanian, Judah Gamliel Hahn
Life of this patent
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Abstract
A memory system may use adaptive trimming to control throughput and traffic from the host to/from the memory. The trimming parameters of memory may be adaptively changed based on the data rate from the host. The programming speed may be slowed in order to reduce wear and improve endurance. In particular, the data rate for the transfer of data from a data buffer to the memory (e.g. NAND flash) may be matched to the host data rate. This programming speed reduction may be triggered upon prediction of idle times in the host bus.
Claims20
A method for adaptive trimming on flash memory, the method comprising:
- receiving write commands from a host;
- detecting write traffic throughput from the host to a memory buffer;
- detecting, by firmware, a detune ratio corresponding to the traffic throughput;
- and
- trimming, according to at least one trim parameter, a traffic throughput from the memory buffer to the flash memory based on the detected detune ratio and based on a priority of the write commands, wherein the priority is designated by and received from the host, wherein the traffic throughput from the memory buffer to the flash memory is trimmed to be closer to the traffic throughput from the host to the memory buffer when the write commands are not a high priority, wherein the at least one trim parameter is adjusted based on a host idle time.
A storage device comprising:
- a non-volatile memory;
- a buffer for storing data to be written to the non-volatile memory;
- a buffer monitor module that monitors a data transfer rate for the data to be stored at the buffer;
- and
- a trim adjustment module that identifies future idle time from a host device providing commands to the storage device that is based on identifying a queue from multiple host side queues, and adjusts a data transfer rate from the buffer to the non-volatile memory from a first trim set to a second trim set that is based on a detune ratio detected by firmware and based on the identified future idle time, wherein the first trim set comprises a standard data transfer rate from the buffer to the non-volatile memory and the second trim set comprises a slower data transfer rate from the buffer to the non-volatile memory, further wherein data written using the second trim set is stored in a different set of blocks in the non-volatile memory from data written using the first trim set, wherein the second trim set is adjusted based on the future idle time of the host, wherein the detune ratio is detected by the firmware in response to the monitored data transfer rate to the buffer.
A memory system for improving memory endurance, the system comprising:
- a flash memory module;
- a staging buffer that receives data to be written to the flash memory module;
- a monitor that monitors a transfer rate of data transferred to fill the staging buffer and monitors a queue for data to be written;
- and
- a flash trim adjuster that reduces a transfer rate, according to a parameter detune ratio detected by firmware, from the staging buffer to the flash memory module based on the monitored transfer rate of the data transferred to the staging buffer and based on a future idle time identified by a power state from the host, wherein the transfer rate from the staging buffer to the flash memory module is not reduced when the queue for the data to be written includes a long queue depth, wherein the at least one trim parameter is adjusted based on the future idle time, wherein the firmware is configured to detect the detune ratio in response to the monitored transfer rate, and wherein data written at the reduced transfer rate is stored in memory blocks separate from other data.
Dependencies are inferred from the claim text.