Quasi-synchronous protocol for large bandwidth memory systems

A high-bandwidth memory (HBM) system, comprising:

• an HBM device;
• and
• a logic circuit comprising a first interface comprising a command/address bus capable of being coupled to a host device and a data bus capable of being coupled to the host device, a second interface coupled to the HBM device, and a transaction bus capable of being coupled to a host device, the logic circuit capable of receiving a first command from the host device through the first interface and converting the received first command to a first processing-in-memory (PIM) command that is sent to the HBM device through the second interface, the first PIM command having a non-deterministic latency for completion, and the logic circuit sending an indication to the host device over the transaction bus when the first PIM command has completed.

A high-bandwidth memory (HBM) system, comprising:

• an HBM device capable of processing-in-memory (PIM) functionality;
• and
• a logic circuit comprising a first interface comprising a command/address bus capable of being coupled to a host device and a data bus capable of being coupled to the host device, a second interface coupled to the HBM device, and a transaction bus capable of being coupled to a host device, the logic circuit capable of receiving a first command from the host device through the first interface and converting the received first command to a first command that is sent to the HBM device through the second interface for PIM processing, the first command having a deterministic latency for completion, and the logic circuit further capable of receiving a second command from the host device through the first interface and converting the received second command to a second command that is sent to the HBM device through the second interface for PIM processing, the second command having a non-deterministic latency for completion.