Memory system with threaded transaction support

A memory system comprising:

• a system substrate;
• a first buffered memory module coupled to the system substrate;
• and
• a second buffered memory module coupled to the system substrate;
• wherein each of the first and second buffered memory modules include
• a module substrate;
• first and second memory devices disposed on the module substrate;
• and
• buffer circuitry disposed on the substrate and coupled to the first and second memory devices via respective first and second secondary data interfaces, the buffer circuitry including a primary data interface for coupling to a group of data links formed on the system substrate, the primary data interface operating at a primary data rate and the first and second secondary data interfaces operating at a secondary data rate;
• error coding circuitry to process data transfers via the primary and/or secondary interface in accordance with an error code;
• and
• wherein during a first mode of operation, the primary interface data rate is at least twice the secondary data rate, and wherein first column data transferred via the first secondary interface overlaps second column data transferred via the second secondary interface.

A memory controller for controlling at least one buffered memory module, the buffered memory module including buffer circuitry and first and second secondary interfaces coupled to respective first and second memory devices, the memory controller comprising:

• a controller primary signaling interface for coupling to at least one buffered memory module via a group of data links;
• command generation circuitry for dispatching command signals to the least one buffered memory module;
• error detection/correction (EDC) circuitry to perform error detection/correction on data transferred on the primary signaling interface;
• and
• wherein, during a first mode of operation, a primary data rate of the controller primary signaling interface is twice a secondary data rate of the first and second secondary interfaces.