Memory system and method for controlling nonvolatile memory
AssigneeToshiba Memory Corporation
InventorShinichi Kanno
Life of this patent
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Abstract
According to one embodiment, a memory system is configured to operate as one of semiconductor storage devices in a storage array. The memory system includes a nonvolatile memory and a controller. The controller executes a write operation of writing data, received from a host, to the nonvolatile memory, and an internal operation for managing the memory system. When starting the internal operation, the controller estimates a value related to an amount of reduction in performance of the write operation due to the start of the internal operation, based on content of the started internal operation, and notifies the host or one or more other semiconductor storage devices of the estimated value.
Claims18
A storage array connectable to a host, the storage array comprising:
- a plurality of memory systems including a first memory system and a second memory system, the first memory system including:
- a nonvolatile memory;
- and
- a controller electrically connected to the nonvolatile memory and configured to execute a write operation of writing data, received from the host, to the nonvolatile memory, and an internal operation, wherein
- when starting the internal operation, the controller of the first memory system:
- estimates one of (i) a reduced write throughput obtained after write throughput of the first memory system has reduced due to a start of the internal operation, and (ii) an amount of reduction in the write throughput due to the start of the internal operation, on the basis of content of the started internal operation;
- and
- notifies the second memory system of the estimated reduced write throughput or the estimated amount of reduction in the write throughput.
A storage array connectable to a host, the storage array comprising:
- a plurality of memory systems including a first memory system and a second memory system, the first memory system including:
- a nonvolatile memory;
- and
- a controller electrically connected to the nonvolatile memory and configured to execute a write operation of writing data, received from the host, to the nonvolatile memory, and an internal operation, the internal operation including a garbage collection operation of the nonvolatile memory, a thermal protection operation for preventing excessive heating of the first memory system, and a power restriction operation for suppressing power consumption of the first memory system to be less than a maximum power allowed thereto, wherein
- when starting one of the garbage collection operation, the thermal protection operation and the power restriction operation, the controller of the first memory system:
- estimates one of (i) a reduced write throughput obtained after write throughput of the first memory system has reduced due to a start of the one of the garbage collection operation, the thermal protection operation, and the power restriction operation, and (ii) an amount of reduction in the write throughput due to the start of the one of the garbage collection operation, the thermal protection operation, and the power restriction operation;
- and
- notifies the second memory system of the estimated reduced write throughput or the estimated amount of reduction in the write throughput, and factor data indicating which one of the garbage collection operation, the thermal protection operation and the power restriction operation is a cause for the reduction in the write throughput.
A method for controlling a storage array that includes a plurality of memory systems including a first memory system and a second memory system, the method comprising:
- executing a write operation for writing data, received from a host, to a nonvolatile memory in the first memory system;
- executing an internal operation for managing the first memory system;
- estimating one of (i) a reduced write throughput obtained after write throughput of the first memory system has reduced due to a start of the internal operation, and (ii) an amount of reduction in the write throughput due to the start of the internal operation, when the internal operation is started;
- and
- notifying the second memory system of the estimated reduced write throughput or the estimated amount of reduction in the write throughput.
Dependencies are inferred from the claim text.