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US 10,591,983 B2Granted
Computer accelerator system using a trigger architecture memory access processor
AssigneeWisconsin Alumni Research Foundation
InventorsChen-Han Ho, Karthikeyan Sankaralingam, Sung Kim
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Abstract
A specialized memory access processor is placed between a main processor and accelerator hardware to handle memory access for the accelerator hardware. The architecture of the memory access processor is designed to allow lower energy memory accesses than can be obtained by the main processor in providing data to the hardware accelerator while providing the hardware accelerator with a sufficiently high bandwidth memory channel. In some embodiments, the main processor may enter a sleep state during accelerator calculations to substantially lower energy consumption.
Claims20
A computer comprising:
- a first processor communicating with an external memory and including circuitry to provide execution of a first set of standard computer instructions and circuitry for an exchange of data with the external memory;
- a second processor communicating with the first processor including circuitry to provide execution of a second set of accelerator computer instructions providing the execution of functions at an accelerated rate compared to the execution of those functions on the first processor;
- a third processor communicating with the first processor and the second processor and including instruction storage circuitry and execution circuitry to provide for the execution of a set of memory access instructions held in the instruction storage circuitry, the third processor operating to:
- (1) be configured by the first processor to receive the set of memory access instructions from the first processor into the instruction storage circuitry, the set of memory access instructions including:
- (a) multiple event instructions defining events that will trigger actions needed for accessing memory,
- (b) multiple action instruction defining data transfer operations,
- (c) multiple initialization values operated on by the event instructions including base addresses, and
- (d) multiple calculations needed for computation of memory addresses;
- and
- (2) after configuration by the first processor to execute the memory access instructions in the instruction storage circuitry using the execution circuitry to exchange data between the second processor and external memory during operation of the second processor the exchange of data being according to the event instructions and action instructions describing data transfer operations operating on memory locations defined by the initialization values.
7 more elements
A method of executing a program using a computer having:
- a first processor communicating with an external memory and including circuitry to provide execution of a first set of standard computer instructions and circuitry for an exchange of data with the external memory;
- a second processor communicating with the first processor including circuitry to provide execution of a second set of accelerator computer instructions providing the execution of functions at an accelerated rate compared to the execution of those functions on the first processor;
- and
- a third processor communicating with the first processor and the second processor and including instruction storage circuitry and execution circuitry to provide for the execution of a set of memory access instructions held in the instruction storage circuitry, the third processor operating to receive the set of memory access instructions from the first processor, the set of memory access instructions including:
- (a) multiple event instructions defining events that will trigger actions needed for accessing memory,
- (b) multiple action instruction defining data transfer operations,
- (c) multiple initialization values operated on by the event instructions including base addresses, for programming of the third processor to exchange data between the second processor and external memory during operation of the second processor;
- a
- (d) multiple calculations needed for computation of memory addresses;
- and
- the method comprising the steps of:
- (a) executing a program by the first processor to a beginning of an acceleration region of the program where faster execution could be provided by the second processor;
- (b) providing multiple event instructions by the first processor defining events that will trigger actions needed for accessing memory, multiple action instruction defining data transfer operations, multiple initialization values operated on by the event instructions including base addresses, and multiple calculations needed for computation of memory addresses to the third processor for accessing memory for the second processor for execution of the acceleration region;
- and
- (c) after configuration of the third processor by the first processor, executing the memory access instructions in the instruction storage circuitry by the third processor using the execution circuitry to exchange data between the second processor and external memory during operation of the second processor, the exchange of data being according to the event instructions, calculations, and action instructions describing data transfer operations operating on memory locations defined by the initialization values, to execute the acceleration region by the second and third processor and not by the first processor.
12 more elements
Dependencies are inferred from the claim text.