Cache memory with reduced power consumption mode
AssigneeMicrosoft Technology Licensing, LLC
InventorsPatrick P. Lai, Robert Allen Shearer
Life of this patent
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AssigneeMicrosoft Technology Licensing, LLC
InventorsPatrick P. Lai, Robert Allen Shearer
Estimating the term…
Processors may include cache circuitry that is a significant source of power consumption. A cache is going to be placed into a lower power mode. Based at least in part on this anticipated transition, the contents of the cache data lines are copied into persistent storage. While the cache is in the lower power mode, the tag circuitry is kept operational. When an access request is made to the cache, a relatively fast lookup of the tag in the tag array can be made. The location where the associated cache line is stored in the persistent storage may be determined from the tag data. Upon a tag hit, the system is able to find the contents of the requested cache line in the persistent storage without returning the storage array of the cache to a fully operational state.
An apparatus for processing data, comprising:
A method of operating a cache memory system, comprising:
A method of operating a processing system, comprising:
Dependencies are inferred from the claim text.