Memory access management for low-power use cases of a system on chip via secure non-volatile random access memory

A system for managing low-power use cases of a system on chip, the system comprising:

• means for booting a system on chip (SoC) comprising a plurality of SoC processing devices, the SoC comprising a circuit board with the plurality of SoC processing devices mounted thereon;
• means for creating a trusted channel to a secure non-volatile random access memory (NVRAM), the secure NVRAM located off-chip relative to the SoC;
• means for determining a power-saving software program to be executed on the SoC by one of the plurality of SoC processing devices by assessing a hint received from the power-saving software program and assessing a trait about the power-saving software program, each hint corresponding to a fixed value and each trait comprising a measurement made by hardware about the power-saving software program;
• means for loading a software image associated with the power-saving software program from volatile memory to the secure NVRAM;
• and
• means for powering down each of the plurality of SoC processing devices except the one executing the software image from the secure NVRAM in response to loading the software image to the secure NVRAM.

A system for managing memory access for low-power use cases of a system on chip, the system comprising:

• a system on chip (SoC) comprising a plurality of SoC processing devices, the SoC comprising a circuit board with the plurality of SoC processing devices mounted thereon;
• a double data rate (DDR) memory electrically coupled to the SoC;
• a secure non-volatile random access memory (NVRAM) having a fuse with a pass gate value for creating a trusted channel;
• and
• a low-power use case management module comprising logic configured to:
• determine a power-saving software program to be executed on the SoC by one of the plurality of SoC processing devices by assessing a hint received from the power-saving software program and assessing a trait about the power-saving software program, each hint corresponding to a fixed value and each trait comprising a measurement made by hardware about the power-saving software program;
• load a software image associated with the power-saving software program from the DDR memory to the secure NVRAM;
• and
• in response to loading the software image to the secure NVRAM, initiating a powering down of each of the plurality of SoC processing devices except the one executing the software image from the secure NVRAM.

A computer program embodied in a non-transitory computer-readable medium and executable by a processor for managing memory access for low-power use cases of a system on chip, the computer program comprising logic configured to:

• boot a system on chip (SoC) comprising a plurality of SoC processing devices, the SoC comprising a circuit board with the plurality of SoC processing devices mounted thereon;
• create a trusted channel to a secure non-volatile random access memory (NVRAM) the secure NVRAM located off-chip relative to the SoC;
• determine a power-saving software program to be executed on the SoC by one of the plurality of SoC processing devices by assessing a hint received from the power-saving software program and assessing a trait about the power-saving software program, each hint corresponding to a fixed value and each trait comprising a measurement made by hardware about the power-saving software program;
• load a software image associated with the power-saving software program from volatile memory to the secure NVRAM;
• and
• in response to loading the software image to the secure NVRAM, power down each of the plurality of SoC processing devices except the one executing the software image from the secure NVRAM.