Configurable mapping of timer channels to protection groups
AssigneeRenesas Electronics America Inc.
InventorJon Matthew Brabender
Life of this patent
Estimating the term…
Abstract
An apparatus and method for mapping timer channels to protection groups. One embodiment of the method can be implemented in a microcontroller unit (MCU) that comprises a central processing unit (CPU) coupled to a plurality of timer channels and a plurality of programmable group output disable (PTGOD) circuits. The CPU can select a first group of the timer channels to respond to an assertion of a first output disable signal from a first of the PTGOD circuits. Each timer channel of the first group can disable an output signal in response to receiving the assertion of the first output disable signal.
Claims20
A method implemented in a microcontroller unit (MCU) that comprises a central processing unit (CPU) coupled to a plurality of timer channels having respective control registers and a plurality of programmable timer group output disable (PTGOD) circuits, the method comprising:
- the CPU programming a first group of the timer channels by writing first timer control values to the respective control registers of the timer channels of the first group;
- asserting, by a first of the PTGOD circuits, a first output disable signal to the first group;
- using, by each timer channel of the first group, the first timer control value that has been programmed into its respective control register by the CPU to determine whether it will be disabled in response to the assertion of the first output disable signal by the first of the PTGOD circuits;
- each timer channel of the first group generating a respective pulse width modulated (PWM) signal;
- and
- in response to the first output disable signal being asserted:
- if the first timer control value of one timer channel of the first group has a first logic value, outputting, by the one timer channel, the respective PWM signal;
- and
- if the first timer control value of the one timer channel of the first group has a second logic value, preventing output, by the one timer channel, of the respective PWM signal.
A system comprising:
- a microcontroller (MCU), wherein the MCU comprises:
- a central processing unit (CPU);
- a plurality of timer channels, each timer channel including a respective control register;
- and
- a plurality of programmable timer group output disable (PTGOD) circuits,
- wherein the CPU is configured to program a first group of the timer channels by writing first timer control values to the respective control registers of the timer channels of the first group, and
- wherein a first of the PTGOD circuits is configured to assert a first output disable signal to the first group, and
- wherein each timer channel of the first group is configured to use the first timer control value that has been programmed into its respective control register by the CPU to determine whether it will be disabled in response to the assertion of the first output disable signal by the first of the PTGOD circuits, and
- wherein each timer channel of the first group is further configured to generate a respective pulse width modulated (PWM) signal, and
- wherein in response to the first output disable signal being asserted:
- if the first timer control value of one timer channel of the first group has a first logic value, the one timer channel is configured to output the respective PWM signal;
- and
- if the first timer control value of the one timer channel of the first group has a second logic value, the one timer channel is configured to prevent output of the respective PWM signal.
A microcontroller comprising:
- a plurality of timer channels, each timer channel including a respective control register;
- a plurality of programmable timer group output disable (PTGOD) circuits;
- and
- a memory comprising an embedded program, the embedded program, when executed by a CPU of the microcontroller, causes the microcontroller to perform a method comprising:
- programming a first group of the timer channels by writing first timer control values to the respective control registers of the timer channels of the first group,
- wherein a first of the PTGOD circuits is configured to assert a first output disable signal to the first group, and
- wherein each timer channel of the first group is configured to use the first timer control value that has been programmed into its respective control register by the CPU to determine whether it will be disabled in response to the assertion of the first output disable signal by the first of the PTGOD circuits, and
- wherein each timer channel of the first group is further configured to generate a respective pulse width modulated (PWM) signal, and
- wherein in response to the first output disable signal being asserted:
- if the first timer control value of one timer channel of the first group has a first logic value, the one timer channel is configured to output the respective PWM signal;
- and
- if the first timer control value of the one timer channel of the first group has a second logic value, the one timer channel is configured to prevent output of the respective PWM signal.
Dependencies are inferred from the claim text.