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US 10,591,792 B2Granted
Liquid crystal display panel and device
AssigneeShenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
InventorSikun Hao
Life of this patent
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Abstract
A liquid crystal display panel and device is provided. In the panel, a gate electrode of a first thin-film transistor of a pixel at (n)th row and (2k+1)th column connects to a second scan line of pixels in (n−1)th row, a source electrode of the first thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to a corresponding common line, and a drain electrode of the first thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to a pixel at (n)th row and (2k+1)th column.
Claims16
A liquid crystal display panel, comprising:
- a plurality of data lines;
- a plurality of scan lines;
- m common lines;
- and
- a plurality of pixels forming N rows of pixels and M columns of pixels, each pixel comprising a first thin-film transistor and a second thin-film transistor, each row of pixels corresponding to two scan lines including a first scan line and a second scan line, every two columns of pixels corresponding to one data line, each common line corresponding to at least one column of pixels, the common line configured to input a common voltage;
- wherein a gate electrode of the first thin-film transistor of a pixel at (n)th row and (2k+1)th column connects to the second scan line of pixels in (n−1)th row, a source electrode of the first thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to a corresponding common line, a drain electrode of the first thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to the pixel at (n)th row and (2k+1)th column;
- wherein a gate electrode of the first thin-film transistor of a pixel at (n)th row and (2k)th column connects to the first scan line of pixels in (n)th row, a source electrode of the first thin-film transistor of the pixel at (n)th row and (2k)th column connects to a corresponding common line, a drain electrode of the first thin-film transistor of the pixel at (n)th row and (2k)th column connects to the pixel at (n)th row and (2k)th column, where 0<n<N, N≥2, 0≤k≤(M−1)/2, M≥m≥2;
- wherein a gate electrode of the second thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to the first scan line of the pixels in (n)th row, a source electrode of the second thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to a corresponding data line, a drain electrode of the second thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to the pixel at (n)th row and (2k+1)th column;
- wherein a gate electrode of the second thin-film transistor of the pixel at (n)th row and (2k)th column connects to the second scan line of the pixels in (n)th row, a source electrode of the second thin-film transistor of the pixel at (n)th row and (2k)th column connects to a corresponding data line, a drain electrode of the second thin-film transistor of the pixel at (n)th row and (2k)th column connects to the pixel at (n)th row and (2k)th column;
- and
- wherein pixels in a first column correspond to a first common line and pixels in an (M)th column correspond to an (m)th common line;
- for pixels in a second column to an (M−1)th column, every two columns of pixels correspond to one common line.
9 more elements
A liquid crystal display panel, comprising:
- a plurality of data lines;
- a plurality of scan lines;
- m common lines;
- and
- a plurality of pixels forming N rows of pixels and M columns of pixels, each pixel comprising a first thin-film transistor and a second thin-film transistor, each row of pixels corresponding to two scan lines including a first scan line and a second scan line, every two columns of pixels corresponding to one data line, each common line corresponding to at least one column of pixels, the common line configured to input a common voltage;
- wherein a gate electrode of the first thin-film transistor of a pixel at (n)th row and (2k+1)th column connects to the second scan line of pixels in (n−1)th row, a source electrode of the first thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to a corresponding common line, a drain electrode of the first thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to the pixel at (n)th row and (2k+1)th column;
- and
- wherein a gate electrode of the first thin-film transistor of a pixel at (n)th row and (2k)th column connects to the first scan line of pixels in (n)th row, a source electrode of the first thin-film transistor of the pixel at (n)th row and (2k)th column connects to a corresponding common line, a drain electrode of the first thin-film transistor of the pixel at (n)th row and (2k)th column connects to the pixel at (n)th row and (2k)th column, where 0<n<N, N≥2, 0≤k≤(M−1)/2, M≥m≥2,
- wherein a gate electrode of the second thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to the first scan line of the pixels in (n)th row, a source electrode of the second thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to a corresponding data line, a drain electrode of the second thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to the pixel at (n)th row and (2k+1)th column;
- and
- a gate electrode of the second thin-film transistor of the pixel at (n)th row and (2k)th column connects to the second scan line of the pixels in (n)th row, a source electrode of the second thin-film transistor of the pixel at (n)th row and (2k)th column connects to a corresponding data line, a drain electrode of the second thin-film transistor of the pixel at (n)th row and (2k)th column connects to the pixel at (n)th row and (2k)th column.
8 more elements
A liquid crystal display device, comprising:
- a backlight module;
- and
- a liquid crystal display panel, comprising:
- a plurality of data lines;
- a plurality of scan lines;
- m common lines;
- and
- a plurality of pixels forming N rows of pixels and M columns of pixels, each pixel comprising a first thin-film transistor and a second thin-film transistor, each row of pixels corresponding to two scan lines including a first scan line and a second scan line, every two columns of pixels corresponding to one data line, each common line corresponding to at least one column of pixels, the common line configured to input a common voltage;
- wherein a gate electrode of the first thin-film transistor of a pixel at (n)th row and (2k+1)th column connects to the second scan line of pixels in (n−1)th row, a source electrode of the first thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to a corresponding common line, a drain electrode of the first thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to the pixel at (n)th row and (2k+1)th column;
- and
- wherein a gate electrode of the first thin-film transistor of a pixel at (n)th row and (2k)th column connects to the first scan line of pixels in (n)th row, a source electrode of the first thin-film transistor of the pixel at (n)th row and (2k)th column connects to a corresponding common line, a drain electrode of the first thin-film transistor of the pixel at (n)th row and (2k)th column connects to the pixel at (n)th row and (2k)th column, where 0<n<N, N≥2, 0≤k≤(M−1)/2, M≥m≥2,
- wherein a gate electrode of the second thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to the first scan line of the pixels in (n)th row, a source electrode of the second thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to a corresponding data line, a drain electrode of the second thin-film transistor of the pixel at (n)th row and (2k+1)th column connects to the pixel at (n)th row and (2k+1)th column;
- and
- a gate electrode of the second thin-film transistor of the pixel at (n)th row and (2k)th column connects to the second scan line of the pixels in (n)th row, a source electrode of the second thin-film transistor of the pixel at (n)th row and (2k)th column connects to a corresponding data line, a drain electrode of the second thin-film transistor of the pixel at (n)th row and (2k)th column connects to the pixel at (n)th row and (2k)th column.
11 more elements
Dependencies are inferred from the claim text.