Input shift register having parallel serial scan outputs, command output
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
Claims12
A test architecture within an integrated circuit comprising:
- (a) logic circuitry having parallel stimulus data inputs and parallel response data outputs;
- (b) parallel scan paths having serial scan inputs for receiving stimulus data, serial scan outputs for outputting response data, parallel stimulus data outputs coupled to the parallel stimulus data inputs, and parallel response data inputs coupled to the parallel response data outputs;
- (c) an input shift register having a serial input, parallel outputs coupled to the serial scan inputs, and a command output separate from the parallel outputs;
- and
- (d) an output shift register having parallel inputs coupled to the serial scan outputs and a serial output.
Dependencies are inferred from the claim text.