Compressed scan chains with three input mask gates and registers

An electronic scan circuitry comprising:

• (a) decompressor circuitry having a serial data input line and parallel data output lines;
• (b) scan chains, each scan chain having a scan chain input coupled to one parallel data output line and having a scan chain output;
• (c) first masking circuitry having first masking inputs coupled to a first group of the scan chain outputs, the first masking circuitry including:
• (i) first gates, each first gate having a first input connected to a first masking input, a second input coupled to a first qualify line, a third input, and a first masking output;
• and
• (ii) first registers coupled in series, each first register having a serial input and an output connected to the third input of a first gate;
• (d) second masking circuitry having second masking inputs coupled to a second group of the scan chain outputs, the second masking circuitry including:
• (i) second gates, each second gate having a first input connected to a second masking input, a second input coupled to a second qualify line separate from the first qualify line, a third input, and a second masking output;
• and
• (ii) second registers coupled in series with the first registers, each second register having a serial input and an output connected to a third input of the second gates;
• and
• (e) compactor circuitry having parallel compactor inputs coupled to the first masking outputs and the second masking outputs, and having a serial compactor output.