Sleek serial interface for a wrapper boundary register (device and method)

A serially-operable interface device on a chip (1), the interface device (201) for generating control signals for a Wrapper Boundary Register (40;

• WBR) on chip (1,1*) level, said wrapper control signals (30) complying with a given standard for testing a core device (100), said core device provided on the chip (1) as well and having the WBR (40), the chip (1;1*) comprising:
• one physical Data Input (1a) for test purposes and one physical Data Output (1b) for test purposes and no more than an input and an output terminal of the serial interface device (201) are coupled to the terminals (1a, 1b) on said chip (1) containing the interface device (201) and the core device (100) with the WBR;
• and
• a physical Clock Input (1c) for test purposes that is coupled to a third terminal (1c) on said chip (1;1*) on chip level for supplying a clock signal (SCLK) to the serial interface device (201);
• the serial interface device (201) on chip further comprising an Instruction Register (213) to receive and hold wrapper-instructions supplied through the physical data input terminal (1a);
• wherein the state machine (210) is configured to:
• read a currently active wrapper-instruction, as held by the Instruction Register (213);
• and
• generate and provide on-chip wrapper control signals (30) of the given standard for the core device (100) having the Wrapper Boundary Register (40;
• WBR) according to the wrapper-instruction read from the Instruction Register (213).

A device for testing a plurality of wrapped cores within a System-on-Chip, wherein:

• each wrapped core of the plurality of wrapped cores within the System-on-Chip comprises an associated serial interface device directly controlled by a single off-chip test master, thereby controlling all of the plurality of wrapped cores within the System-on-Chip by the single off-chip test master;
• each serial interface device having a unique device address, the device address being an own device address for addressing each individual serial interface device;
• each serial device has a structure, and the structure of all of the serial devices is the same;
• and
• the off-chip test master is configured to operate in parallel all serial interface devices as multiple slaves and elects from said multiple slaves one thereof as a targeted slave by sending the device address of the targeted slave.