Systems and methods to generate a test bench for electrostatic discharge analysis of an integrated circuit design

A system for circuit design, comprising:

• one or more computers comprising a non-transitory machine-readable media configured to store a netlist file comprising data records of a plurality of circuit devices and a plurality of nets interconnecting the plurality of circuit devices, wherein the netlist file forms a device under test (DUT);
• at least one computer of the one or more computers, the at least one computer coupled to the non-transitory machine readable media storing the netlist file and comprising a processor configured to:
• calculate a plurality of parameters associated respectively with a plurality of injection pins of the DUT based upon data records of at least a corresponding portion of the plurality of circuit devices and the plurality of nets;
• generate a plurality of pin-specific test benches, including a first test bench comprising a first resistance inductance capacitance (RLC) circuit for a first injection pin based on a first parameter and a second test bench comprising a second RLC circuit for a second injection pin based on a second parameter;
• transmit an electrostatic discharge (ESD) stimulus from the RLC circuit to the first injection pin of the DUT;
• and
• in response to determining by the processor that the ESD stimulus discharged through a ground pin of the DUT:
• generate an indication that the DUT has passed an ESD analysis test on the first injection pin.

A computer readable non-transitory medium containing one or more computer instructions, which when executed by a processor cause the processor to:

• receive a netlist file comprising data records of a plurality of circuit devices and a plurality of nets interconnecting the plurality of circuit devices, wherein the netlist file forms a device under test (DUT);
• calculate a first parameter associated with a first injection pin of the DUT based upon data records of at least a portion of the plurality of circuit devices and the plurality of nets;
• generate a first test bench comprising a resistance inductance capacitance (RLC) circuit for the first injection pin based on the first parameter;
• transmit an electrostatic discharge (ESD) stimulus from the RLC circuit to the first injection pin of the DUT;
• in response to determining by the processor that the ESD stimulus discharged through a ground pin of the DUT:
• generate an indication that the DUT has passed an ESD analysis test on the first injection pin;
• and
• generate a second test bench comprising a second RLC circuit for the second injection pin based on a second parameter associated with a second injection pin of the DUT.