Interposer with multiplexers, stimulus and control generators, and tap circuitry

A test interposer comprising:

• (A) an interposer substrate having a first face and a second face, the interposer substrate having through input vias and through output vias, the vias having contact points on the first and second faces;
• (B) a first multiplexer having a first input coupled with a contact point on the first face, a second input, a control input, and an output coupled with a contact point on the second face;
• (C) a second multiplexer having a first input coupled with a contact point on the first face, a second input, a control input, and an output coupled with a contact point on the second face;
• (D) stimulus generator circuitry having a first control input, a second control input, and an output coupled with the second input of the first multiplexer;
• (E) control generator circuitry having a control input, a control output coupled with the first control input of the stimulus generator circuitry, a second output coupled with the second input of the second multiplexer circuitry;
• and
• (F) test access port circuitry having a test data input, a test clock input, a test mode select input, and a test data output, the test access port circuitry having control leads coupled to the first multiplexer, the second multiplexer, the stimulus generator circuitry, and the control generator circuitry.