US 10,587,250 B2 · Current-starving in tunable-length delay (TLD) circuits employable in adaptive clock distribution (ACD) systems for compensating supply voltage droops in integrated circuits (ICs)

Abstract

Current-starving in tunable-length delay (TLD) circuits in adaptive clock distribution (ACD) systems for compensating voltage droops in clocked integrated circuits (ICs) is disclosed. Voltage droops slow propagation of signals in clocked circuits. However, clock delay circuits in a TLD circuit increase a clock period by increasing a clock delay in response to a voltage droop. In large power distribution networks (PDN), impedance can delay and reduce the magnitude of voltage droops experienced at the TLD circuit. If the voltage droop at the TLD circuit is smaller than at the clocked circuit, then the clock period isn't stretched enough to compensate the slowed clocked circuit. A current-starved TLD circuit starves the clock delay circuits of current in response to a voltage droop indication, which further increases the clock signal delay, and further stretches the clock period to overcome a larger voltage droop in clocked circuits in other areas of the IC.

Claims28

Dependent claims

A current-starved tunable-length delay (TLD) circuit for delaying a clock signal distributed in an adaptive clock distribution (ACD) system to a clocked circuit, the current-starved TLD circuit comprising:

a clock delay circuit comprising a clock input configured to receive a clock signal;
and
a current-starving circuit, comprising:
a power input coupled to a power rail;
a current output coupled to the clock delay circuit;
a droop indicator input configured to receive a droop indicator indicating a voltage droop status of a voltage droop in a supply voltage;
a current-starving control circuit configured to generate a current-starving control indicator in response to the droop indicator;
and
a current supply circuit configured to selectively starve current supplied on the current output coupled to the clock delay circuit in response to the current-starving control indicator indicating the voltage droop status of the voltage droop in the supply voltage;
the clock delay circuit configured to generate a delayed clock signal based on a delay of the clock signal based on the selectively starved current;
wherein:
the current supply circuit comprises a plurality of current paths, each current path of the plurality of current paths comprising:
a power supply input coupled to the power input of the current-starving circuit;
a power output coupled to the current output of the current-starving circuit;
and
a control input configured to receive the current-starving control indicator;
and
each current path of the plurality of current paths is configured to selectively supply current from the power supply input to the power output based on the current-starving control indicator.

15 more elements

A method of current-starving a tunable-length delay (TLD) circuit in an adaptive clock distribution (ACD) system, comprising:

receiving a clock signal;
receiving a droop indicator indicating a voltage droop status of a voltage droop in a supply voltage;
generating a current-starving control indicator in response to the droop indicator indicating the voltage droop status of the voltage droop in the supply voltage;
selectively starving current supplied to a clock delay circuit in response to the current-starving control indicator indicating the voltage droop status;
and
generating a delayed clock signal based on a delay of the clock signal in the clock delay circuit based on the selectively starved current;
wherein:
generating the current-starving control indicator comprises:
generating the current-starving control indicator indicating a first current supply state in response to the droop indicator indicating a no voltage droop state;
and
generating the current-starving control indicator indicating a second current supply state in response to the droop indicator indicating the no voltage droop state;
and
the method further comprises:
supplying current on a first one among a plurality of current paths, in response to the current-starving control indicator indicating the first current supply state;
and
supplying current to a second one among the plurality of current paths, in response to the current-starving control indicator indicating the second current supply state.

13 more elements

An adaptive clock distribution (ACD) system for slowing a frequency of a clock signal distributed to a clocked circuit, the ACD system comprising:

a droop detector circuit configured to detect a voltage droop in a supply voltage at a power rail, and generate a droop indicator indicating a voltage droop status of the voltage droop in the supply voltage;
a current-starved tunable-length delay (TLD) circuit, comprising:
a clock delay circuit comprising a clock input configured to receive a clock signal;
and
a current-starving circuit comprising:
a current-starving control circuit configured to generate a current-starving control indicator in response to the droop indicator;
and
a current supply circuit configured to selectively starve current to the clock delay circuit in response to the current-starving control indicator indicating the voltage droop status of the voltage droop in the supply voltage;
the clock delay circuit configured to generate a delayed clock signal based on a delay of the clock signal based on the selectively starved current;
wherein:
the current supply circuit comprises a plurality of current paths, each current path of the plurality of current paths comprising:
a power supply input coupled to a power input of the current-starving circuit;
a power output coupled to a current output of the current-starving circuit;
and
a control input configured to receive the current-starving control indicator;
and
each current path of the plurality of current paths is configured to selectively supply current from the power supply input to the power output based on the current-starving control indicator.

14 more elements

Dependencies are inferred from the claim text.

Current-starving in tunable-length delay (TLD) circuits employable in adaptive clock distribution (ACD) systems for compensating supply voltage droops in integrated circuits (ICs)

Life of this patent

Current-starving in tunable-length delay (TLD) circuits employable in adaptive clock distribution (ACD) systems for compensating supply voltage droops in integrated circuits (ICs)

Life of this patent

Abstract

Claims28