Biased amplifier
AssigneeTexas Instruments Incorporated
InventorSudheer Prasad
Life of this patent
Estimating the term…
Abstract
In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.
Claims20
An amplifier, comprising:
- a bias circuit configured to generate a bias voltage with respect to ground;
- and
- an open-loop gain stage comprising:
- a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS) having a gate terminal coupled to a first node, a source terminal coupled to a second node, a drain terminal coupled to a third node, and a bulk connection coupled to the bias circuit;
- a second PMOS having a gate terminal coupled to a ground node, a source terminal coupled to the second node, a drain terminal coupled to a fourth node, and a bulk connection coupled to the bias circuit;
- a first n-type MOSFET (NMOS) having a drain terminal and a gate terminal coupled to the third node and a source terminal coupled to a fifth node;
- a second NMOS having a drain terminal coupled to the fourth node, a gate terminal coupled to the third node;
- and a source terminal coupled to the fifth node, wherein the gain stage is configured to couple to an adjustable resistor positioned between the third node and the fourth node;
- and
- a buffer stage coupled to the open-loop gain stage at the fourth node and comprising a super source follower.
An integrated circuit comprising:
- an input node;
- an output node;
- a gain stage coupled to the input node, wherein the gain stage includes:
- a first transistor that includes a gate coupled to the input node, a source coupled to a second node, and a drain coupled to a third node;
- a second transistor that includes a gate coupled to a ground node, a source coupled to the second node, and a drain coupled to a fourth node;
- a third transistor that includes a gate coupled to the third node, a drain coupled to the third node, and a source coupled to the ground node;
- and
- a fourth transistor that includes a gate coupled to the third node, a drain coupled to the fourth node, and a source coupled to the ground node;
- a bias circuit coupled to a bulk connection of the first transistor and to a bulk connection of the second transistor;
- and
- a buffer stage coupled to the fourth node of the gain stage, wherein the buffer stage includes:
- a fifth transistor that includes a gate coupled to the fourth node, a source coupled to the output node, and a drain coupled to a seventh node;
- and
- a sixth transistor that includes a gate coupled to the bias circuit, a source coupled to the ground node, and a drain coupled to the seventh node.
An integrated circuit comprising:
- a capacitive sensor;
- and
- an amplifier circuit coupled to the capacitive sensor, wherein the amplifier circuit includes:
- a gain stage that includes:
- a first p-type transistor having a gate terminal coupled to an input node to which the capacitive sensor is coupled, a source terminal coupled to a second node by a first resistor, and a drain terminal coupled to a third node;
- a second p-type transistor having a gate terminal coupled to a ground node, a source terminal coupled to the second node by a second resistor, and a drain terminal coupled to a fourth node;
- a first n-type transistor having a gate terminal coupled to the third node, a source terminal coupled to the ground node, and a drain terminal coupled to the third node;
- a second n-type transistor having a gate terminal coupled to the third node, a source terminal coupled to the ground node, and a drain terminal coupled to the fourth node;
- and
- an impedance element coupled between the third node and the fourth node;
- a buffer stage coupled to the fourth node;
- and
- a bias circuit coupled to a bulk of the first p-type transistor and to a bulk of the second p-type transistor.
Dependencies are inferred from the claim text.