Parallel computing

A processor for executing a computer program, the processor comprising a plural number of computing units and an interconnect connected to the computing units, wherein each computing unit comprises a processing unit and a memory having at least two memory ports, each port assignable to one or more respective regions of the memory, wherein each computing unit is configured to:

• perform an initial step of the program to write:
• an initial output value to an output region of the memory, and an initial input value to an input region of the memory;
• and
• perform a subsequent step of the program by:
• in a compute phase:
• assign one of the two ports to both the input region and the output region;
• execute code sequences on the processing unit to compute an output set of one or more new output values, and write the output set to the output region, the output set computed from the initial output and initial input values, each of which is retrieved via said one port in the compute phase;
• when the compute phase has completed, in an exchange phase:
• assign a first of the two ports to the output region and a second of the two ports to the input region;
• and
• retrieve a new output value of the output set from the output region via said first port and send the retrieved value to a different computing unit via the interconnect, and receive via the interconnect a new input value which has been computed by different computing unit in the subsequent step and write the received value to the input region via said second port.

A computer program product comprising executable instructions of a computer program configured, when execute on a processor comprising a plural number of computing units and an interconnect connected to the computing units, wherein each computing unit comprises a processing unit and a memory having at least two memory ports, each port assignable to one or more respective regions of the memory, to cause the processor to perform the following operations at each computing unit:

• performing an initial step of the program to write:
• an initial output value to an output region of the memory, and an initial input value to an input region of the memory;
• and
• performing a subsequent step of the program by:
• in a compute phase:
• assigning one of the two ports to both the input region and the output region;
• executing code sequences on the processing unit to compute an output set of one or more new output values, and writing the output set to the output region, the output set computed from the initial output and initial input values, each of which is retrieved via said one port in the compute phase;
• when the compute phase has completed, in an exchange phase:
• assigning a first of the two ports to the output region and a second of the two ports to the input region;
• and
• retrieving a new output value of the output set from the output region via said first port and sending the retrieved value to a different computing unit via the interconnect, and receiving via the interconnect a new input value which has been computed by a different computing unit in the subsequent step and writing the received value to the input region via said second port.

A computing unit for use in a processor for executing a computer program, the computing unit comprising a processing unit and a memory having at least two memory ports, each port assignable to one or more respective regions of the memory, the computing unit being configured to:

• perform an initial step of the program to write:
• an initial output value to an output region of the memory, and an initial input value to an input region of the memory;
• and
• perform a subsequent step of the program by:
• in a compute phase:
• assign one of the two ports to both the input region and the output region;
• execute code sequences on the processing unit to compute an output set of one or more new output values, and write the output set to the output region, the output set computed from the initial output and initial input values, each of which is retrieved via said one port in the compute phase;
• when the compute phase has completed, in an exchange phase:
• assign a first of the two ports to the output region and a second of the two ports to the input region;
• and
• retrieve a new output value of the output set from the output region via said first port and send the retrieved value to a different computing unit via an interconnect of the processor, and receive via the interconnect a new input value which has been computed by a different computing unit in the subsequent step and write the received value to the input region via said second port.