Dual-rail transceiver with improved signal-to-noise ratio for differential high-speed links
AssigneeNVIDIA Corporation
InventorsSanquan Song, Nikola Nedovic
Life of this patent
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Abstract
A signal transceiver includes a signal transmitter driving a first differential link between a supply voltage of the signal transmitter and a fraction of the supply voltage, and driving a second differential link between the faction of the supply voltage and a reference ground. The signal transceiver also includes a signal receiver in which the first differential link is coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor; and the second differential link is coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.
Claims20
A signal transceiver comprising:
- a signal transmitter comprising:
- a first differential link configured with a first common mode voltage, the first differential link coupled to a first switch between a supply voltage of the signal transmitter and a fraction of the supply voltage;
- and
- a second differential link configured with a second common mode voltage, the second differential link configured to a second switch between the fraction of the supply voltage and a reference ground;
- a signal receiver comprising:
- the first differential link coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor;
- and
- the second differential link coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.
A signal receiver comprising:
- a first differential link configured with a first common mode voltage
- a second differential link configured with a second common mode voltage;
- and
- the first differential link and the second differential link cross-coupled between a gate node of an NMOS transistor and to a gate node of a PMOS transistor.
A signal transceiver comprising:
- a signal transmitter comprising:
- a first differential link configured with a first common mode voltage, the first differential link operable at voltage levels between a supply voltage of the signal transmitter and one half of the supply voltage;
- and
- a second differential link configured with a second common mode voltage, the second differential link operable between one half of the supply voltage and reference ground;
- a signal receiver configured to extract a bit value communicated as a difference between a first voltage level on the first differential link and a second voltage level on the second differential link.
Dependencies are inferred from the claim text.