Back to results
US 10,581,445 B2Granted
Digitally calibrated successive approximation register analog-to-digital converter
AssigneeAvnera Corporation
InventorsJianping Wen, Garry Link, Wai Laing Lee
Life of this patent
Estimating the term…
Abstract
A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors Cn[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vd and the digital output port.
Claims20
A successive approximation register analog-to-digital converter, comprising:
- a voltage comparator having a first input, a second input, and an output;
- a first plurality of capacitors each having a first plate and a second plate, the first plate in electrical communication with the first input of the voltage comparator and switchably connectable to a common mode voltage, and the second plate switchably connectable to one of a first input voltage, a reference voltage, the common mode voltage, or a ground, and the common mode voltage equal to one-half of the reference voltage;
- a second plurality of capacitors each having a first plate and a second plate, the first plate in electrical communication with the second input of the voltage comparator and switchably connectable to the common mode voltage, the second plate switchably connectable to one of a second input voltage, the reference voltage, the common mode voltage, or the ground, and the first plurality of capacitors and the second plurality of capacitors collectively representing a set of bits;
- and
- a controller configured to implement a collapsible successive approximation register algorithm using balanced ternary values for each bit of the set of bits to encode an analog input.
2 more elements
A successive approximation register analog-to-digital converter, comprising:
- a voltage comparator having a first input, a second input, and an output;
- a first plurality of capacitors each having a first plate and a second plate, the first plate in electrical communication with the first input of the voltage comparator and switchably connectable to a common mode voltage, and the second plate switchably connectable to one of a first input voltage, a reference voltage, the common mode voltage, or a ground, and the common mode voltage equal to one-half of the reference voltage;
- a second plurality of capacitors each having a first plate and a second plate, the first plate in electrical communication with the second input of the voltage comparator and switchably connectable to the common mode voltage, the second plate switchably connectable to one of a second input voltage, the reference voltage, the common mode voltage, or the ground, and the first plurality of capacitors and the second plurality of capacitors collectively representing a set of bits;
- and
- a controller configured to implement a collapsible successive approximation register algorithm that performs a comparison of a conversion residue to a mid-code of at least a portion of one or more least significant bits from the set of bits.
2 more elements
A system configured to convert an analog input to a digital output, the system comprising:
- an analog input port;
- a digital output port;
- and
- a successive approximation register analog-to-digital converter connected between the analog input port and the digital output port, the successive approximation register analog-to-digital converter including:
- a voltage comparator having a first input, a second input, and an output;
- a first plurality of capacitors each having a first plate and a second plate, the first plate in electrical communication with the first input of the voltage comparator and switchably connectable to a common mode voltage, and the second plate switchably connectable to one of a first input voltage, a reference voltage, the common mode voltage, or a ground, and the common mode voltage a fraction of the reference voltage;
- a second plurality of capacitors each having a first plate and a second plate, the first plate in electrical communication with the second input of the voltage comparator and switchably connectable to the common mode voltage, the second plate switchably connectable to one of a second input voltage, the reference voltage, the common mode voltage, or the ground, and the first plurality of capacitors and the second plurality of capacitors collectively representing a set of bits;
- and a controller configured to implement a collapsible successive approximation register algorithm using balanced ternary values for each bit of the set of bits to encode an analog input.
5 more elements
Dependencies are inferred from the claim text.