Clocked frequency detector RF auto-tuning system
AssigneepSemi Corporation
InventorDavid Kovac
Life of this patent
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Abstract
Devices and methods for auto-tuning a tunable circuit based on a frequency of operation of the tunable circuit using a clocked frequency detector circuit are described. The clocked frequency detector uses a readily available clock signal to drive a counter circuit to provide an indication of the frequency of operation of the tunable circuit. The tunable circuit, including the clocked frequency detector, can be integrated within a same chip that is autonomously configurable based on the frequency of operation and the readily available clock.
Claims22
A radio frequency (RF) tunable integrated circuit configured to operate over a frequency range of operation of an input RF signal, comprising:
- one or more tunable elements;
- and
- a clocked frequency detector circuit configured to detect an indication of a frequency of operation, fo, of the input RF signal based on an externally supplied reference clock to the RF tunable integrated circuit,
- wherein tuning of the one or more tunable elements is based on the detected indication of the frequency of operation of the input RF signal, and is configured to provide a tuned frequency dependent performance of an output RF signal of the tunable integrated circuit, and
- wherein the reference clock is a clock used in an interface protocol that comprises one of:
- a) mobile industry processor interface (MIPI), and b) serial peripheral interface (SPI).
A method for tuning a radio frequency (RF) tunable circuit, the method comprising:
- providing a frequency, fr, of a reference clock available on a target system;
- providing a tunable circuit having one or more tunable elements;
- providing a frequency range of operation of an input RF signal to the tunable circuit;
- establishing a number N, N>1, so that for any frequency of operation, fo, within the frequency range of operation, fr>>fo,/N;
- based on the establishing, providing a divide-by-N circuit that is configured to receive the input RF signal and generate therefrom a divide-by-N signal with a frequency of fo/N that is substantially lower than the frequency of the reference clock;
- providing a counter circuit configured to receive the divide-by-N signal and count a number of cycles of the reference clock in a defined number of cycles of the divide-by-N signal;
- and
- monolithically integrating the tunable circuit, the divide-by-N circuit, and the counter circuit in a single integrated circuit,
- wherein during operation of the tunable circuit, tuning of the one or more tunable elements is based on a number of cycles of the reference clock in the defined number of cycles of the divide-by-N signal counted by the counter circuit, and
- wherein the reference clock is a clock used in an interface protocol that comprises one of:
- a) mobile industry processor interface (MIPI), and b) serial peripheral interface (SPI).
A method for tuning a radio frequency (RF) tunable circuit, the method comprising:
- providing a frequency, fr, of a reference clock available on a target system;
- providing a tunable circuit having one or more tunable elements;
- providing a frequency range of operation of an input RF signal to the tunable circuit;
- establishing a number N, N>1, so that for any frequency of operation, fo, within the frequency range of operation, fr<<fo,/N;
- based on the establishing, providing a divide-by-N circuit that is configured to receive the input RF signal and generate therefrom a divide-by-N signal with a frequency of fo/N that is substantially higher than the frequency of the reference clock;
- providing a counter circuit configured to receive the divide-by-N signal and count a number of cycles of the divide-by-N signal in a period of the reference clock, and
- monolithically integrating the tunable circuit, the divide-by-N circuit, and the counter circuit in a single integrated circuit;
- wherein during operation of the tunable circuit, tuning of the one or more tunable elements is based on a number of cycles of the divide-by-N signal in the period of the reference clock counted by the counter circuit, and
- wherein the reference clock is a clock used in an interface protocol of the target system that comprises one of:
- a) mobile industry processor interface (MIPI), and b) serial peripheral interface (SPI).
Dependencies are inferred from the claim text.