High-level synthesis (HLS) method and apparatus to specify pipeline and spatial parallelism in computer hardware

A non-transitory computer-readable storage medium, the medium storing instructions that when executed by a computer system will cause the computer system to:

• in response to a command from a client to commence operations for a digital design flow for a digital system,
• receive producer instructions defining a producer processing thread;
• generate a producer register-transfer level (RTL) description of the producer processing thread;
• receive consumer instructions defining a consumer processing thread;
• generate a consumer RTL description of the consumer processing thread;
• and
• automatically infer generation of streaming hardware RTL in response to receiving the producer and consumer instructions.

A computer-implemented method, comprising:

• performing high-level synthesis (HLS) for a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC) by
• receiving producer instructions including at least a producer Pthread defining a producer processing thread;
• generating a producer register-transfer level (RTL) description of the producer processing thread;
• receiving consumer instructions including at least a consumer Pthread defining a consumer processing thread;
• generating a consumer RTL description of the consumer processing thread;
• and
• automatically inferring generation of streaming hardware RTL in response to receiving the producer and consumer instructions.