Stall logic for a data processing engine in an integrated circuit
AssigneeXilinx, Inc.
InventorsGoran H K Bilski, Juan J. Noguera Serra, Jan Langer, Baris Ozgul
Life of this patent
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Abstract
An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes a core, a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory, and a stall circuit coupled to the core configured to stall or resume the core in response to one or more inputs.
Claims19
A data processing engine (DPE) for a DPE array in an integrated circuit (IC), comprising:
- a core;
- a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE, the data memory including a plurality of random access memory (RAM) banks;
- support circuitry including hardware synchronization circuitry, direct memory access (DMA) circuitry, and arbitration logic each coupled to the data memory;
- and
- a stall circuit coupled to the arbitration logic and the core, the stall circuit configured to stall or resume the core in response to one or more inputs including an input from the arbitration logic that is indicative of a memory collision in the data memory between the core and one or more other cores in the DPE array, the stall circuit further configured to stall or resume one or more of the plurality of RAM banks that provide data to the core.
A method of operating a data processing engine (DPE) for a DPE array in an integrated circuit (IC), the method comprising:
- operating a core and a memory in the DPE, the memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE, the data memory including a plurality of random access memory (RAM) banks;
- stalling the core, and one or more RAM banks of the plurality of RAM banks that provide data to the core, using a stall circuit coupled to the core and the memory in response to one or more inputs by asserting a stall signal based on an indication of a memory collision by arbitration logic configured to arbitrate access to the data memory;
- and
- resuming the core and the one or more RAM banks using the stall circuit.
An integrated circuit (IC), comprising:
- a data processing engine (DPE) array having a plurality of DPEs, each of the plurality of DPEs comprising:
- a core;
- a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE, the data memory including a plurality of random access memory (RAM) banks;
- support circuitry including hardware synchronization circuitry, direct memory access (DMA) circuitry, and arbitration logic each coupled to the data memory;
- and
- a stall circuit coupled to the arbitration logic and the core, the stall circuit configured to stall or resume the core in response to one or more inputs including an input from the arbitration logic that is indicative of a memory collision in the data memory between the core and one or more other cores in the DPE array, the stall circuit further configured to stall or resume one or more of the plurality of RAM banks that provide data to the core.
Dependencies are inferred from the claim text.