Defragmented and efficient micro-operation cache

An integrated circuit comprising:

• a micro-op cache comprising a micro-op tag array and a micro-op data array;
• and
• a cache controller coupled to the micro-op cache, wherein to allocate a first entry to the micro-op cache, the cache controller is to:
• allocate indexing metadata of the first entry to the micro-op tag array according to a plurality of sets of ways of set-associative cache;
• and
• allocate a plurality of micro-ops to the micro-op data array according to an index within the micro-op data array, the index comprising bank number of a plurality of physical cache banks and a set within one physical cache bank of the plurality of physical cache banks of the micro-op data array, wherein allocation to the micro-op data array is according to sequential bank numbers of the plurality of physical cache banks.

A method comprising:

• allocating, by a cache controller of a processor, indexing metadata of a first entry to a micro-op tag array of a micro-op cache according to a plurality of sets of ways of set-associative cache;
• and
• allocating, by the cache controller, a plurality of micro-ops of the first entry to a micro-op data array of the micro-op cache, wherein allocating the plurality of micro-ops is according to an index comprising bank number of a plurality of physical cache banks and a set within one physical cache bank of the plurality of physical cache banks of the micro-op data array, and
• wherein allocating the plurality of micro-ops to the micro-op data array comprises sequentially allocating each micro-op of the plurality of micro-ops across the plurality of physical cache banks according to a sequential bank number.