High dynamic range CTIA pixel

A pixel having an associated pixel frame period comprising a reset phase followed by an integration phase, comprising:

• an input node for connection to the photocurrent output Iph of a photodiode;
• an output node, the voltage at said output node being Vout;
• a capacitive transimpedance amplifier (CTIA), comprising:
• an amplifier having at least an inverting input port and an output port, the inverting input port of said amplifier connected to said input node and the output port of said amplifier connected to said output node;
• a first integration capacitor connected between said input node and said output node;
• and
• a first reset switch connected between said input node and said output node;
• a second integration capacitor connected between said input node and a first node, the voltage at said first node being Vlg;
• a second reset switch connected between said first node and said output node;
• and
• a first FET connected across said second reset switch and driven with a DC voltage Vclamp;
• wherein said pixel has an associated pixel saturation level, said pixel frame period arranged such that:
• said first and second reset switches are closed during said reset phase;
• said first and second reset switches are opened during said integration phase;
• said first FET is driven with a DC gate voltage Vclamp such that:
• said first FET is off during said reset phase;
• and
• said first FET conditionally turns on during said integration phase;
• and
• Vout is sampled just before the end of said integration phase.

A pixel having an associated pixel frame period comprising a reset phase followed by an integration phase and a charge redistribution phase, comprising:

• an input node for connection to the photocurrent output Iph of a photodiode;
• an output node, the voltage at said output node being Vout;
• a capacitive transimpedance amplifier (CTIA), comprising:
• an amplifier having at least an inverting input port and an output port, the inverting input port of said amplifier connected to said input node and the output port of said amplifier connected to said output node;
• a first integration capacitor connected between said input node and said output node;
• and
• a first reset switch connected between said input node and said output node;
• a second integration capacitor connected between said input node and a first node, the voltage at said first node being Vlg;
• a second reset switch connected between said first node and said output node;
• and
• a first FET connected across said second reset switch and driven with a drive voltage Ven_lg;
• wherein said pixel has an associated pixel saturation level, said pixel frame period arranged such that:
• said first and second reset switches are closed during said reset phase;
• said first and second reset switches are opened during said integration phase;
• said second reset switch is closed during said charge redistribution phase;
• said first FET is driven with a gate voltage Vclamp during said reset and integration phases such that:
• said first FET is off during said reset phase;
• and
• said first FET conditionally turns on during said integration phase;
• and
• said first FET is driven with a full-rail gate voltage during said charge redistribution phase such that said first FET turns on in strong inversion and acts as a switch that is closed, thereby forcing Vlg and Vout to become equal;
• Vout is sampled a first time just before the end of the integration phase, this sampling constituting the high-gain CTIA output;
• and
• Vout is sampled a second time just before the end of the charge redistribution phase, this sampling constituting the low-gain CTIA output.