Modifying a circuit design

A method for modifying circuits comprising:

• detecting, by one or more processors, negative paths for a circuit design based on a circuit timing test of the circuit design, wherein the negative paths correspond to at least one of logic design flaws, integration design flaws or macro design flaws;
• detecting, by the one or more processors, a priority of the logic design flaws, the integration design flaws, and the macro design flaws;
• assigning, by the one or more processors, the negative paths to a logic bucket, an integration bucket, or a macro bucket based on the priority, wherein the logic bucket corresponds to the logic design flaws, the integration bucket corresponds to the integration design flaws, and the macro bucket corresponds to the macro design flaws and design flaws residing within a macro of the circuit design;
• detecting, by the one or more processors, a modification to the circuit design based on the logic design flaws, the integration design flaws, and the macro design flaws;
• and
• applying, by the one or more processors, the modification to the circuit design to enable manufacturing of an integrated circuit, wherein an overall delay between two latches of the integrated circuit is below a predetermined threshold.

A computer program product for modifying circuits, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processor, to cause the processor to:

• detect negative paths for a circuit design based on a circuit timing test of the circuit design, wherein the negative paths correspond to at least one of logic design flaws, integration design flaws or macro design flaws;
• detect a priority of the logic design flaws, the integration design flaws, and the macro design flaws;
• assign each the negative paths to a logic bucket, an integration bucket, or a macro bucket based on the priority, wherein the logic bucket corresponds to the logic design flaws, the integration bucket corresponds to the integration design flaws, and the macro bucket corresponds to the macro design flaws or and design flaws residing within a macro of the circuit design;
• detect a modification to the circuit design based on the logic design flaws, the integration design flaws, and the macro design flaws;
• and
• apply the modification to the circuit design to enable manufacturing of an integrated circuit, wherein an overall delay between two latches of the integrated circuit is below a predetermined threshold.