High frame rate video compatible with existing receivers and amenable to video decoder implementation

An apparatus comprising:

• a memory;
• and
• one or more processors configured to execute instructions stored in the memory, the instructions comprising:
• receiving a first bitstream having a first packet identifier (“PID”) and a second bitstream having a second PID;
• decoding the first bitstream using a first decoder;
• decoding the second bitstream using a second decoder, the second decoder being different from the first decoder;
• interleaving the decoded first bitstream and the decoded second bitstream to form a high frame rate video signal, wherein interleaving the decoded first bitstream and the decoded second bitstream comprises combining the decoded first bitstream and the decoded second bitstream in a common output pipeline, and wherein the high frame rate video signal has a frame rate equal to the sum of the frame rate of the decoded first bitstream and the decoded second bitstream;
• and
• repeating each frame of the first bitstream to form the high frame rate video signal when the second decoded bitstream is not present.