Signal processing device and method, imaging element, and electronic device

A signal processing device, comprising:

• a gray code counter;
• a column analog to digital (A/D) conversion unit, wherein the column A/I) conversion unit includes:
• a higher bit binary counter;
• and
• a lower bit gray code latch, wherein a gray code clock signal generated by the gray code counter is supplied to the lower bit gray code latch, wherein the lower bit gray code latch generates gray codes on the basis of the gray code clock signal and converts gray codes into binary codes to generate lower bits of a binary code that are supplied to the higher bit binary counter, and
• wherein the lower bit gray code latch includes:
• a plurality of latches, wherein the number of latches is equal to the number of bits of gray code clocks supplied from the gray code counter, wherein respective bits of the gray code clocks supplied from the gray code counter are supplied to the corresponding latches, and wherein the lower bit gray code latch supplies a carry signal to the higher bit binary counter in synchronization with a clock signal provided to one of the latches of the lower bit gray code latch via a signal line.

An image sensor, comprising:

• a pixel array;
• a column-parallel processing unit, including:
• a gray code counter;
• a plurality of column analog to digital (A/D) conversion units, wherein each of the column A/D conversion units includes:
• a higher bit binary counter;
• and
• a lower bit gray code latch, wherein a gray code clock signal generated by the gray code counter is supplied to the lower bit gray code latch, and wherein the lower bit gray code latch generates gray codes on the basis of the gray code clock signal and converts gray codes into binary codes to generate lower bits of a binary code that are supplied to the higher bit binary counter;
• wherein the lower bit gray code latch includes:
• a plurality of latches, wherein the number of latches is equal to the number of bits of gray code clocks supplied from the gray code counter, and wherein respective bits of the gray code clocks supplied from the gray code counter are supplied to the corresponding latches;
• and
• a metastable countermeasure latch, wherein the metastable countermeasure latch supplies a carry signal to the higher bit binary counter;
• and
• a control unit, wherein the control unit supplies a control signal to the column-parallel processing unit.