Packet accelerator ingress communication processor peripheral streaming interface, scheduler, buffer
AssigneeTexas Instruments Incorporated
InventorsAmritpal Singh Mundra, Denis Roland Beaudoin
Life of this patent
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Abstract
An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
Claims5
An accelerated cryptographic engine comprising:
- (a) a packet accelerator ingress communication processor peripheral interface streaming interface having a streaming data input and having a first output and a second output;
- (b) a packet header processor having an input and having an output;
- (c) scheduler circuitry having a first input coupled to the first output of the packet accelerator ingress communication processor peripheral interface streaming interface, having a second input, having a third input, and having an output;
- (d) first buffer circuitry having an input coupled to the second output of the packet accelerator ingress communication processor peripheral interface streaming interface, and having an output coupled to the second input of the scheduler circuitry;
- and
- (e) second buffer circuitry having an input coupled to the output of the packet header processor and having an output coupled to the third input of the scheduler circuitry.
Dependencies are inferred from the claim text.