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US 10,567,163 B2Granted
Processor with secure hash algorithm and digital signal processing method with secure hash algorithm
AssigneeVia Alliance Semiconductor Co., Ltd.
InventorZhi Zhang
Life of this patent
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Abstract
A processor using an internal memory to store constants Kt required in a secure hash algorithm (SHA). The latency due to loading the constants Kt from an external memory, therefore, is eliminated. The processor further introduces an instruction set architecture that provides one instruction for the processor to read the constants Kt from the internal memory and perform a particular process on the read constants Kt. Thus, the SHA works efficiently.
Claims18
A processor device, comprising:
- an internal memory, storing an array of constants Kt required in a secure hash algorithm, where iterations in each loop of the secure hash algorithm are numbered by t, and t changes from 0 to a natural number (L−1) during each loop of the secure hash algorithm;
- and
- a set of execution units, including an execution unit group required in the secure hash algorithm,
- wherein:
- the execution unit group retrieves the constants Kt from the internal memory to update working variables used in the secure hash algorithm;
- the constants Kt are factory burned-in values in the internal memory to be directly retrieved by the execution unit group, wherein a total number n of the constants Kt are organized such that each of the constants Kt with a bit length m can be obtained by retrieving the m bits from a fractional part of each cube root of a set of first n prime numbers;
- the execution unit group receives a get-value W+K instruction;
- and
- a read address of at least one of the constants Kt is directly contained in the get-value W+K instruction for the execution unit group to retrieve at least one of the constants Kt from the internal memory.
6 more elements
A digital signal processing method, comprising:
- providing an internal memory within a processor, wherein the internal memory stores an array of constants Kt required in a secure hash algorithm, iterations in each loop of the secure hash algorithm are numbered by t, and t changes from 0 to a natural number (L−1) during each loop of the secure hash algorithm;
- and
- using a set of execution units of the processor to provide an execution unit group required in the secure hash algorithm, wherein the execution unit group retrieves the constants Kt from the internal memory to update working variables used in the secure hash algorithm,
- wherein:
- the constants Kt are factory burned-in values in the internal memory to be directly retrieved by the execution unit group, wherein a total number n of the constants Kt are organized such that each of the constants Kt with a bit length m can be obtained by retrieving the m bits from a fractional part of each cube root of a set of first n prime numbers;
- the execution unit group receives a get-value W+K instruction;
- and
- a read address of at least one of the constants Kt is directly contained in the get-value W+K instruction for the execution unit group to retrieve at least one of the constants Kt from the internal memory.
5 more elements
Dependencies are inferred from the claim text.