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US 10,567,161 B2Granted
Architecture and instruction set for implementing advanced encryption standard AES
AssigneeIntel Corporation
InventorsShay Gueron, Wajdi K. Feghali, Vinodh Gopal
Life of this patent
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Abstract
A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
Claims21
A processor comprising:
- a plurality of cores;
- a level 1 (L1) instruction cache to store instructions;
- a level 1 (L1) data cache to store data;
- instruction fetch circuitry to fetch the instructions from the L1 instruction cache;
- decode circuitry to decode a Single Instruction Multiple Data (SIMD) Advanced Encryption Standard (AES) instruction specifying that only a single AES round is to be performed, wherein the SIMD AES instruction has an encrypt/decrypt parameter that is dedicated to specification of whether either one of encryption and decryption is to be performed;
- a Read Only Memory (ROM) to store micro-operations for the SIMD AES instruction;
- a first 128-bit source register to store first input data;
- a second 128-bit source register to store second input data;
- and
- an execution unit including AES execution circuitry, wherein, in response to execution of the SIMD AES instruction and specification by the encrypt/decrypt parameter that the decryption is to be performed, the AES execution circuitry is to execute the micro-operations to perform a plurality of operations to perform only a single AES decryption round, including an exclusive OR (XOR) of the first input data and the second input data, an inverse byte substitution transform, and an inverse shift rows transform.
7 more elements
A processor comprising:
- a level 1 (L1) instruction cache to store instructions;
- a level 1 (L1) data cache to store data;
- an instruction decoder to decode a Single Instruction Multiple Data (SIMD) Advanced Encryption Standard (AES) instruction to control that only a single AES round is to be performed, wherein the SIMD AES instruction has an encrypt/decrypt parameter that is dedicated to controlling whether either one of decryption and encryption is to be performed;
- a Read Only Memory (ROM) to store micro-operations for the SIMD AES instruction;
- a scheduler to schedule operations for execution;
- a first 128-bit source register to store first input data;
- a second 128-bit source register to store second input data;
- and
- an execution unit including AES execution circuitry, wherein, in response to the SIMD AES instruction and the encrypt/decrypt parameter controlling that the decryption is to be performed, the execution unit is to execute the micro-operations to perform a plurality of operations to perform only a single AES decryption round, including an exclusive OR (XOR) of the first input data and the second input data, an inverse byte substitution transform, an inverse shift rows transform, and write a result of the SIMD AES instruction to a 128-bit destination storage location.
6 more elements
A processor comprising:
- a level 1 (L1) instruction cache to store instructions;
- a level 1 (L1) data cache to store data;
- an instruction decoder to decode a Single Instruction Multiple Data (SIMD) Advanced Encryption Standard (AES) instruction controlling that a single AES round is to be performed, wherein the SIMD AES instruction has a given parameter that is capable of being configured to select either one of decryption and encryption to be performed;
- a Read Only Memory (ROM) to store micro-operations for the SIMD AES instruction;
- a scheduler to schedule operations for execution;
- a first 128-bit source register to store first input data;
- a second 128-bit source register to store second input data;
- an execution unit including AES execution circuitry, wherein, in response to the SIMD AES instruction and the given parameter being configured to select that the decryption is to be performed, the execution unit is to execute the micro-operations to perform a plurality of operations to perform a single AES decryption round, including an exclusive OR (XOR) of the first input data and the second input data, an inverse byte substitution transform that is to substitute bytes using data retrieved from a substitution table, an inverse shift rows transform that is to shift data in each row of a first array by a specified amount to produce a second array, and store a result of the SIMD AES instruction;
- and
- a retirement unit.
7 more elements
Dependencies are inferred from the claim text.