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US 10,567,160 B2Granted
Architecture and instruction set for implementing advanced encryption standard (AES)
AssigneeIntel Corporation
InventorsShay Gueron, Wajdi K. Feghali, Vinodh Gopal
Life of this patent
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Abstract
A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
Claims22
A processor comprising:
- a plurality of cores, a first core of the plurality of cores including:
- a level 1 (L1) instruction cache to store instructions;
- a level 1 (L1) data cache to store data;
- instruction fetch circuitry to fetch the instructions from the L1 instruction cache;
- decode circuitry to decode an Advanced Encryption Standard (AES) instruction, the AES instruction controlling that only a single AES round is to be performed, wherein the AES instruction is a Single Instruction Multiple Data (SIMD) instruction, and wherein the AES instruction has an encrypt/decrypt parameter that is dedicated to specification of whether either one of encryption or decryption is to be performed;
- a first 128-bit source register to store first input data;
- a second 128-bit source register to store second input data;
- and
- an execution unit including AES execution circuitry, wherein, in response to execution of the AES instruction and specification by the encrypt/decrypt parameter that the encryption is to be performed, the AES execution circuitry is to perform a plurality of operations to perform only a single AES encryption round, including an exclusive OR (XOR) of the first input data and the second input data, a byte substitution transform, and a shift rows transform.
6 more elements
A processor comprising:
- a level 1 (L1) instruction cache to store instructions;
- a level 1 (L1) data cache to store data;
- an instruction decoder to decode an Advanced Encryption Standard (AES) instruction specifying that only a single AES round is to be performed, wherein the AES instruction is a Single Instruction Multiple Data (SIMD) instruction, and wherein the AES instruction has an encrypt/decrypt parameter that is able to select either one of encryption or decryption is to be performed;
- a Read Only Memory (ROM) to store micro-operations for the AES instruction;
- a scheduler to schedule operations for execution;
- a first 128-bit source register to store first input data;
- a second 128-bit source register to store second input data;
- and
- an execution unit including AES execution circuitry, wherein, in response to execution of the AES instruction and selection of the encryption by the encrypt/decrypt parameter, the execution unit is to execute the micro-operations to perform a plurality of operations to perform only a single AES encryption round, including an exclusive OR (XOR) of the first input data and the second input data, a byte substitution transform, a shift rows transform, and storage of a result of the AES instruction.
6 more elements
A processor comprising:
- a level 1 (L1) instruction cache to store instructions;
- a level 1 (L1) data cache to store data;
- an instruction decoder to decode an Advanced Encryption Standard (AES) instruction specifying that only a single AES round is to be performed, wherein the AES instruction is a Single Instruction Multiple Data (SIMD) instruction, and wherein the AES instruction has a parameter that is dedicated to specification of whether either one of encryption or decryption is to be performed;
- a Read Only Memory (ROM) to store micro-operations for the AES instruction;
- a scheduler to schedule operations for execution;
- a first 128-bit source register to store first input data;
- a second 128-bit source register to store second input data;
- an execution unit including AES execution circuitry, wherein, in response to execution of the AES instruction and specification of the encryption by the parameter, the execution unit is to execute the micro-operations to perform a plurality of operations to perform only a single AES encryption round, including an exclusive OR (XOR) of the first input data and the second input data, a byte substitution transform that is to substitute bytes using data retrieved from a substitution table, a shift rows transform that is to shift data in each row of a first array by a specified amount to produce a second array, and storage of a result of the AES instruction;
- and
- a retirement unit.
7 more elements
Dependencies are inferred from the claim text.