Method and circuits for phase-locked loops

A phase lock loop (PLL) circuit for synthesizing a clock signal from an incoming data stream, the PLL circuit comprising:

• a binary phase detector configured to generate a first polarity signal and a second polarity signal based on incoming data stream and a feedback signal, the first and second polarity signals respectively indicating whether the incoming data stream is leading the feedback signal, or whether the feedback signal is leading the incoming data stream;
• a digital filter coupled to the binary phase detector and configured to:
• receive the first polarity signal and the second polarity signal, and
• filter the first polarity signal such that a filtered first polarity signal is generated on a first path and a second path, the first and second paths being different;
• and
• filter the second polarity signal such that a filtered second polarity signal is generated on a third path and a fourth path, the third and fourth paths being different;
• a charge pump coupled to the digital filter and configured to:
• receive the filtered first polarity signal on the second path,
• receive the filtered second polarity signal on the third path;
• and
• integrate the filtered first polarity signal and the filtered second polarity signal such that an integral signal is generated;
• and
• an oscillator coupled to the charge pump and the digital filter, the oscillator configured to receive the integral signal from the charge pump,
• receive, from the digital filter, the filtered first polarity signal on the first path;
• receive, from the digital filter, the filtered second polarity signal on the fourth path, and
• generate the synthesized clock signal, wherein the oscillator is configured such that a frequency of the synthesized clock signal is controlled by the integral signal as well as the filtered first and second polarity signals received, wherein the oscillator includes an inverter that receives the filtered first polarity signal on the first path;
• and wherein the synthesized clock signal is looped back to the binary phase detector as the feedback signal.