Device and method of processing a data word using checkbits
AssigneeInfineon Technologies AG
InventorsThomas Kern, Roland Brachmann, Michael Goessel
Life of this patent
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Abstract
A method is proposed for processing a data word, in which the data word comprises a first partial data word and a second partial data word, in which first checkbits are defined for the first partial data word, wherein the first partial data word and the first checkbits form a first codeword, in which second checkbits are defined for the second partial data word, wherein the second partial data word and the second checkbits form a second codeword, in which third checkbits are defined for the data word, wherein at least (i) the data word, (ii) a linking of the first checkbits with the second checkbits, and (iii) the third checkbits are parts of a third codeword.
Claims33
A method for processing a data word that comprises a first partial data word and a second partial data word, comprising:
- defining first checkbits for the first partial data word using a first partial circuit, wherein the first partial data word and the first checkbits form a first codeword of the data word,
- defining second checkbits for the second partial data word using a second partial circuit, wherein the second partial data word and the second checkbits form a second codeword of the data word,
- defining third checkbits for the data word using a third partial circuit, wherein at least the data word, a linking of the first checkbits with the second checkbits, and the third checkbits are parts of a third codeword of the data word.
A method for processing a data word, wherein the data word comprises a first partial data word and a second partial data word, comprising:
- defining a first bit sequence at least on the basis of first checkbits and the first partial data word using a first partial circuit,
- checking whether the first bit sequence is a codeword,
- if the first bit sequence is not a codeword:
- performing an error correction of the data word at least on the basis of the first checkbits and further checkbits,
- wherein the further checkbits are defined using the first checkbits.
A circuit arrangement for processing a data word, wherein the data word comprises a first partial data word and a second partial data word, wherein the circuit arrangement comprises:
- a first partial circuit configured to define first checkbits for the first partial data word, wherein the first partial data word and the first checkbits form a first codeword of the data word,
- a second partial circuit configured to define second checkbits for the second partial data word, wherein the second partial data word and the second checkbits form a second codeword of the data word,
- a third partial circuit configured to define third checkbits for the data word, wherein at least the data word, a linking of the first checkbits with the second checkbits, and the third checkbits are parts of a third codeword of the data word.
A device for processing a data word, wherein the data word comprises a first partial data word and a second partial data word, wherein the device comprises a processing unit which is configured in hardware or is configured to receive instructions from a memory that upon execution of the instructions is configured to:
- define a first bit sequence at least based on first checkbits and the first partial data word,
- check whether the first bit sequence is a codeword,
- if the first bit sequence is not a codeword:
- perform an error correction of the data word at least based on the first checkbits and further checkbits,
- wherein the further checkbits are defined using the first checkbits.
Dependencies are inferred from the claim text.