List decode circuits
AssigneeHewlett Packard Enterprise Development LP
InventorChris Michael Brueggen
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Abstract
Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a list decode circuit may include a syndrome calculation circuit, a symbol erasure circuit, an erasure syndrome calculation circuit and a Berlekamp-Massey algorithm circuit (BMA), and an error locator polynomial (ELP) evaluation circuit. The syndrome calculation circuit may calculate a baseline syndrome and erasure syndrome calculation circuit may calculate erasure syndromes from error locator polynomials calculated by the symbol erasure circuit. The BMA circuit may use the calculated syndromes to generate a series of ELPs, which may be used by the ELP evaluation circuit to identify error locations in a codeword.
Claims14
A list decode circuit, comprising:
- a syndrome calculation circuit to calculate a baseline syndrome for a codeword provided by a plurality of memory devices;
- a symbol erasure circuit to, for each of the plurality of memory devices:
- generate a symbol group erasure iteration of the codeword by erasing a symbol group contributed by the memory device to the codeword;
- and
- calculate erasure locator polynomials for the symbol group erasure iteration of the codeword;
- an erasure syndrome calculation circuit to calculate erasure syndromes for each symbol group erasure iteration of the codeword based on the corresponding erasure locator polynomial and the baseline syndrome;
- a Berlekamp-Massey algorithm (BMA) circuit to generate a series of error locator polynomials (ELPs) by processing trial decodes of each symbol group erasure iteration of the codeword in parallel using erasure syndromes corresponding to the symbol group erasure iterations of the codeword, the BMA circuit being pipelined such that trial decodes are initiated on back-to-back clock cycles;
- and
- an ELP evaluation circuit to identify error locations in the codeword by evaluating each generated ELP over a plurality of values in a finite field in parallel, each of the plurality of values corresponding to a possible error location in the codeword.
A list decode circuit, comprising:
- a syndrome calculation circuit to calculate a baseline syndrome for a codeword provided by a plurality of memory devices;
- a symbol erasure circuit to, for each of the plurality of memory devices:
- generate a symbol group erasure iteration of the codeword by erasing a symbol group contributed by the memory device to the codeword;
- and
- calculate erasure locator polynomials for the symbol group erasure iteration of the codeword;
- an erasure syndrome calculation circuit to calculate erasure syndromes for each symbol group erasure iteration of the codeword based on the corresponding erasure locator polynomial and the baseline syndrome;
- a Berlekamp-Massey algorithm (BMA) circuit to generate a series of error locator polynomials (ELPs) by processing a trial non-erasure decode and trial erasure decodes of each symbol group erasure iteration of the codeword in parallel, the BMA circuit to initiate processing of the trial non-erasure decode before initiating the trial erasure decodes, the BMA circuit being pipelined such that the trial erasure decodes are initiated on back-to-back clock cycles;
- and
- an ELP evaluation circuit to identify error locations in the codeword by evaluating each generated ELP over a plurality of values in a finite field in parallel, each of the plurality of values corresponding to a possible error location in the codeword.
Dependencies are inferred from the claim text.